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PDF IDT74ALVCH162721 Data sheet ( Hoja de datos )
| Número de pieza | IDT74ALVCH162721 | |
| Descripción | 3.3V CMOS 20-BIT FLIP-FLOP | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74ALVCH162721
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
IDT74ALVCH162721
FEATURES:
– 0.5 MICRON CMOS Technology
– Typical tSK(0) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
www.DataSh–eet40U.6.3c5ommm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
– VCC = 3.3V ± 0.3V, Normal Range
– VCC = 2.7V to 3.6V, Extended Range
– VCC = 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH162721:
– Balanced Output Drivers: ±12mA
– Low switching noise
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
Functional Block Diagram
OE 1
56
CLK
29
CLKEN
55
D1
DESCRIPTION:
This 20-bit flip-flop is built using advanced dual metal CMOS technol-
ogy. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type
flip-flops with qualified clock storage. On the positive transition of the
clock (CLK) input, the device provides true data at the Q outputs if the
clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the 20 outputs in either a
normal logic state (high or low) or a high-impedance state. In the high-
impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup compo-
nents. OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in the
high-impedance state.
The ALVCH162721 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
The ALVCH162721 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistor.
CE
C1
1D
2
Q1
To 19 Other Channels
EXTENDED COMMERCIAL TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
1
MARCH 1999
DSC-4566/-
1 page  
IDT74ALVCH162721
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V Unit
2 x Vcc
V
Vcc V
Vcc / 2
V
150 mV
150 mV
30 pF
NEW16link
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
www.DataSTheEetS4UT.comCIRCUITS FOR ALL OUTPUTS
VCC
VLOAD
Open
Pulse(1, 2)
Generator
V IN
VOUT
D.U.T.
500Ω
GND
RT
500Ω
CL
DEFINITIONS:
ALVC Link
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
OUTPUT SKEW - TSK (x)
Switch
VLOAD
GND
Open
INPUT
tPLH1
tPHL1
OUTPUT 1
tSK (x)
tSK (x)
OUTPUT 2
tPLH2
tPHL2
NEW16link
V IH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
ALVC Link
ENABLE AND DISABLE TIMES
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
VIH
VT
0V
OUTPUT
SW ITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT
NORMALLY
SW ITCH
OPEN
HIGH
V L O A D /2
VT
tPHZ
VT
0V
V L O A D /2
VLZ
VOL
VOH
VHZ
0V
NOTE:
ALVC Link
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tREM
tSU tH
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
ALVC Link
PULSE WIDTH
L O W -H IG H -LO W
PULSE
H IG H -L O W -H IG H
PULSE
VT
tW
VT
ALVC Link
tSK(x) = tPLH2 - tPLH1 or tPH L2 - tPHL1
NOTES:
ALVC Link
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74ALVCH162721.PDF ] | |
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