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IDT - (IDT71P71x04) 18Mb Pipelined DDRII SRAM Burst of 2

Numéro de référence IDT71P71804
Description (IDT71P71x04) 18Mb Pipelined DDRII SRAM Burst of 2
Fabricant IDT 
Logo IDT 





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IDT71P71804 fiche technique
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18Mb Pipelined
DDR™II SRAM
Burst of 2
Information
IDT71P71204
IDT71P71104
IDT71P71804
Features
x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
x Common Read and Write Data Port
x Dual Echo Clock Output
x 2-Word Burst on all SRAM accesses
x Multiplexed Address Bus
- One Read or One Write request per clock cycle
www.DataSheet4U.coxm DDR (Double Data Rate) Data Bus
- Two word bursts data per clock
x Depth expansion through Control Logic
x HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
x Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70
ohms
x 1.8V Core Voltage (VDD)
x 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
x JTAG Interface
IDT71P71604
Description
The IDT DDRIITM Burst of two SRAMs are high-speed synchronous
memories with a double-data-rate (DDR), bidirectional data port. This
scheme allows maximization of the bandwidth on the data bus by pass-
ing two data items per clock cycle. The address bus operates at single
data rate speeds, allowing the user to fan out addresses and ease
system design while maintaining maximum performance on data trans-
fers.
The DDRII has scalable output impedance on its data output bus and
echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, indepen-
dent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
Clocking
The DDRII SRAM has two sets of input clocks, namely the K, K clocks
and the C, C clocks. In addition, the DDRII has an output “echo” clock,
CQ, CQ.
The K and K clocks are the primary device input clocks. The K clock
is used to clock in the control signals (LD, R/W and BWx or NWx), the
address, and the first word of the data burst during a write operation.
Functional Block Diagram
DATA
REG
(Note2)
SA
SA0
ADD
REG
(Note2)
LD
R/W
BWx
(Note3)
CTRL
LOGIC
(Note 1)
WRITE DRIVER
18M
MEMORY
ARRAY
(Note1)
(Note4)
(Note1) DQ
K CLK
K GEN
C SELECT OUTPUT CONTROL
C
CQ
CQ
Notes
6112 drw 16
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
MAY 2004
1
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ DSC-6112/00

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