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PDF YMU765 Data sheet ( Hoja de datos )
| Número de pieza | YMU765 | |
| Descripción | Mobile Audio 5 | |
| Fabricantes | Yamaha | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de YMU765 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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YMU765
MA-5
Mobile Audio 5
Outline
www.DataSheet4U.com
YMU765 is a synthesizer LSI for mobile phones that realize advanced game sounds of Java application program etc.
This LSI has a built-in speaker amplifier, and thus, is an ideal device for outputting sounds that are used by mobile
phones in addition to game sounds and ringing melodies that are replayed by a synthesizer.
The synthesizer section adopts the “Stereophonic Hybrid Synthesizer System” which is given advantages of both FM
synthesizers and Wave Table synthesizers to allow simultaneous generation of up to 32 FM voices and 32 Wave Table
voices. Furthermore, the stream playback function, the voice synthesis function by HV (Humanoid Voice) synthesizer
(*), and the time-variant low pass filter function by AL (Analog Lite) synthesizer have also on board.
Since FM synthesizer is able to present countless voices by specifying parameters with only several tens of bytes,
memory capacity and communication band can be saved, and thus, the device exhibits the features in operating
environment of mobile phones such as allowing distribution of arbitrary melodies with voices.
On the other hand, Wave Table synthesizer can pronounce the voice built in ROM and arbitrary ADPCM/PCM voices
from sequencer by the download of the melody with voices etc..
YMU765 has a built-in hardware sequencer that helps to realize a complex play without heavily loading the host CPU.
In addition, it is possible to create more highly efficient applications by the voice synthesis function (*) and the function
of time-variant low pass filter. Moreover, the device also has a built-in circuit for controlling vibrators and LEDs
synchronizing with play of music.
(*) HV synthesizer function only responds to Japanese and Korean language at present.
Features
■ Built-in the hybrid synthesizer, and possible to generate 64 tones simultaneously as maximum.
■ Voice synthesis voice function by HV (Humanoid Voice) synthesizer is on board.
(*) HV synthesizer function only responds to Japanese and Korean language at present.
■ The time fluctuation low pass filter function by AL (Analog Lite) synthesizer is on board.
■ Stream replay with ADPCM / PCM is possible.
■ Has built-in default voices for FM and Wave Table synthesizers in the ROM, and the voices can be downloaded to
RAM.
■ Equipped with speaker amplifier and equalizer circuit.
■ Equipped with a stereophonic output terminal for headphone.
■ Equipped with vibration control circuit, and LED lighting control circuit.
■ Has built-in PLL and inputting of master clock up to 20 MHz is possible and compiles with the TCXO (Temperature
Compensated Crystal Oscillator).
■ Contains a 16-bit stereophonic D/A converter.
■ Has power down mode.
■ Power supply for core
2.65V ∼ 3.30V
■ Power supply for I/O
1.65V ∼ VDD
■ Power supply for speaker amplifier
VDD ∼ 4.50V
■ 32-pin QFN plastic package
YAMAHA CORPORATION
YMU765 CATALOG
CATALOG No : LSI-4MU765A2
2003.7
1 page  
YMU765
Outline of blocks
This section outlines functions of blocks contained in this device and flow of signals.
Clock Input
Clock
Generator
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Instantaneous write path
FIFO
FIFO
Sequencer
Delayed write path
Instantaneous read path
Control
Register
ROM/
RAM
Synthesizer
LED Control
Vibrator Control
Headphone
Output
DAC
EQ
Amp
Speaker
Amp
CPU interface
CPU interface is an 8-bit parallel type.
It assumes that a total of 13 pins of 4 control signals (/WR, /RD, /CS, A0 pin), 8 data bus (D0 to D7), and
1 Interrupt pin (/IRQ) are connected to the external CPU.
This block controls the writing and reading of data by the input polarity of control signal.
Interface register
This register is able to access directly from the external CPU. There are 2 bytes spaces.
The latter Intermediate register can be accessed through the Interface register.
Intermediate register
This register is accessed through the Interface register.
The “Control register” and ROM/SRAM, which describes below, can be accessed through this register.
This register is called the “Intermediate register” since this exists in the middle of the Interface register and the
Control register.
In the Intermediate register, there are some registers to control various functions.
Control register, ROM/SRAM
The Control register and ROM/SRAM are accessed from “Instantaneous write register”, “Delayed write register”, and
“Instantaneous read register” in the Intermediate register.
In the Control register, there is a register to control the following synthesizer mainly.
The voice parameter for FM (GM 128 voices + DRUM 40 voices) and Wave data for WT are stored in ROM.
SRAM is used at the download of arbitrary FM voice parameter and Wave data for WT.
Moreover, it is used as storing buffer at the stream playback of PCM/ADPCM.
FIFO
This is an abbreviation of “First In First Out” means the memory which data is read in order of written.
There are 2 paths to write into FIFO in the Intermediate register.
The “Instantaneous write path” is for accessing the Control register and ROM/SRAM immediately, also “Delayed
write path” is for accessing the Control register after managing time through the sequencer.
FIFO size of Instantaneous path is 64-byte, and its size of Delayed path is 512-byte.
5
5 Page 
YMU765
CPU interface timing
The AC characteristics of a CPU interface are measured on condition as follows.
The input conditions at the time of measurement
The measurement points
: VIH = 0.8×IOVDD,
: VIH = 0.65×IOVDD,
VOH = 0.65×IOVDD,
VIL=0.2×IOVDD
VIL=0.35×IOVDD
VOL=0.35×IOVDD
● CPU interface 1 (In the case of IOVDD≧2.65V)
(Write cycle)
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Item
Address setup time
Address hold time
Chip select setup time
Chip select hold time
Write pulse width
Data setup time
Data hold time
[Condition] TOP=-20 ∼ 85°C,
Symbol
Min
TADS
50
TADH
0
TCSS
50
TCSH
0
TWW
50
TWDS
30
TWDH
0
VDD=IOVDD=2.65 ∼ 3.30V, Capacitor load=50 pF
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
(Read cycle)
Item
Symbol
Min
Access time from /RD pin
TACCRD
Access time from /CS pin
TACCCS
Access time from /A0 pin
TACCA0
Data hold time from /RD pin
TDHRD
0
Data hold time from /CS pin
TDHCS
0
Data hold time from A0 pin
TDHA0
0
High-impedance transition time from /RD pin
TDZRD
High-impedance transition time from /CS pin
TDZCS
[Condition] TOP=-20 ∼ 85°C, VDD=IOVDD=2.65 ∼ 3.30V, Capacitor load=50 pF
IOH= -1.0mA, IOL= +1.0mA (D0 ∼ D7 pin)
Max.
70
70
70
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet YMU765.PDF ] | |
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