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PDF K9F1G08U0A Data sheet ( Hoja de datos )
| Número de pieza | K9F1G08U0A | |
| Descripción | 128M x 8 Bit / 256M x 8 Bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de K9F1G08U0A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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K9F1G08R0A
K9F1G08U0A K9K2G08U1A
Document Title
128M x 8 Bit / 256M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
0.0
0.1
www.DataSheet4U.com
1. Initial issue
1. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns (Page 11, 23~26)
- tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
2. Added Addressing method for program operation
0.2 1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.
0.3 1. PKG(TSOP1, WSOP1) Dimension Change
0.4 1. Technical note is changed
2. Notes of AC timing characteristics are added
3. The description of Copy-back program is changed
4. Voltage range is changed
-1.7V~1.95V -> 1.65V~1.95V
5. Note2 of Command Sets is added
0.5 1. CE access time : 23ns->35ns (p.11)
0.6 1. The value of tREA for 3.3V device is changed.(18ns->20ns)
2. EDO mode is added.
0.7 1. The flow chart to creat the initial invalid block table is cahnged.
Draft Date Remark
Aug. 24. 2003 Advance
Jan. 27. 2004 Preliminary
Apr. 23. 2004 Preliminary
May. 19. 2004 Preliminary
Jan. 21. 2005 Preliminary
Feb. 14. 2005 Preliminary
May. 24. 2005
May 6. 2005
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
1
1 page  
K9F1G08R0A
K9F1G08U0A K9K2G08U1A
PIN CONFIGURATION (ULGA)
www.DataSheet4U.com
K9K2G08U1A-ICB0/IIB0
A B C DE FG HJ K L M N
NC NC
NC
NC NC NC
7
NC
/RE1
/RB2
IO7-2 IO6-2
IO5-2
NC
6
Vcc /RE2 Vss
IO7-1 IO5-1
Vcc
5
4
/CE1 /CE2
/RB1 /WP2 IO6-1
IO4-1 IO4-2
3
CLE1 CLE2 /WE1
IO0-1 IO2-1
Vss
IO3-2
2
Vss ALE2 /WP1 IO1-1 IO3-1 Vss
1
NC
ALE1 /WE2
IO0-2 IO1-2
IO2-2
NC
NC NC NC
NC NC NC
FLASH MEMORY
PACKAGE DIMENSIONS
52-ULGA (measured in millimeters)
Top View
12.00±0.10
#A1
(Datum A)
(Datum B)
A
B
C
D
E
F
G
H
J
K
L
M
N
Bottom View
2.00
7
12.00±0.10
1.00 10.00 1.00
6 54 3 2
1
1.00
1.00
A
B
0.10 C
12-∅1.00±0.05
∅0.1 M C AB
Side View
17.00±0.10
41-∅0.70±0.05
∅0.1 M C AB
5
5 Page 
K9F1G08R0A
K9F1G08U0A K9K2G08U1A
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
K9F1G08R0A
K9F1G08U0A
Max
K9F1G08R0A
K9F1G08U0A
CLE setup Time
tCLS*1
25
15
-
-
CLE Hold Time
tCLH
10
5
-
-
CE setup Time
tCS*1
35
20
-
-
CE Hold Time
tCH 10
5
-
-
WE Pulse Width
tWP 25
15
-
-
ALE setup Time
tALS*1
25
15
-
-
ALE Hold Time
tALH
10
5
-
-
www.DataSheet4U.cDoamta setup Time
tDS*1
20
15
-
-
Data Hold Time
tDH 10
5
-
-
Write Cycle Time
tWC 45
30
-
-
WE High Hold Time
tWH 15
10
-
-
ALE to Data Loading Time
tADL*2
100*2
100*2
-
-
NOTE : 1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
3. For cache program operation, the whole AC Charcateristics must be same as that of K9F1G08R0A.
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay
CLE to RE Delay
Ready to RE Low
RE Pulse Width
WE High to Busy
Read Cycle Time
RE Access Time
CE Access Time
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
Output Hi-Z to RE Low
RE High to WE Low
WE High to RE Low
Device Resetting Time
(Read/Program/Erase)
Symbol
tR
tAR
tCLR
tRR
tRP
tWB
tRC
tREA
tCEA
tRHZ
tCHZ
tOH
tREH
tIR
tRHW
tWHR
tRST
Min
K9F1G08R0A
K9F1G08U0A
--
10 10
10 10
20 20
25 15
--
50 30
--
--
--
--
15 15
15 10
00
100 100
60 60
--
Max
K9F1G08R0A
K9F1G08U0A
25 25
--
--
--
--
100 100
--
30 20
45 35
30 30
20 20
--
--
--
--
--
5/10/500*1
5/10/500*1
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. For cache program operation, the whole AC Charcateristics must be same as that of K9F1G08R0A.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet K9F1G08U0A.PDF ] | |
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