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PDF K4S281632K Data sheet ( Hoja de datos )
| Número de pieza | K4S281632K | |
| Descripción | 128Mb K-die SDRAM | |
| Fabricantes | Samsung | |
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K4S281632K
Industrial Synchronous DRAM
128Mb K-die SDRAM Specification
www.DataSheet4U.com
Industrial Temp. -40 to 85°C
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 of 14
Rev. 1.0 July 2007
1 page  
K4S281632K
4.0 Package Physical Dimension
#54
Industrial Synchronous DRAM
00..02150 TYP
0~8°C
#28
www.DataSheet4U.com
#1
0.10
0.004
MAX
(00..07218)
22.62
0.891
MAX
22.22 ± 0.10
0.875 ± 0.004
#27
0.125+-00..007355
0.005+-00..000031
0.21 ± 0.05
0.008 ± 0.002
1.00 ± 0.10
0.039 ± 0.004
1.20
0.047
MAX
0.30+-00..0150
0.012 +-00..000024
0.80
0.0315
0.05
0.002
MIN
54Pin TSOP(II) Package Dimension
5 of 14
Rev. 1.0 July 2007
5 Page 
K4S281632K
Industrial Synchronous DRAM
14.0 AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
CLK cycle
time
CAS latency=3
CAS latency=2
CLK to valid
output delay
CAS latency=3
CAS latency=2
Output data
hold time
CAS latency=3
CAS latency=2
CLK high pulse width
www.DatCaSLhKeleot4wUp.cuolsme width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output CAS latency=3
in Hi-Z
CAS latency=2
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
60
Min Max
6
1000
-
5
-
2.5
-
2.5
2.5
1.5
1
1
5
-
75
Min Max
7.5
1000
10
5.4
6
3
3
2.5
2.5
1.5
0.8
1
5.4
6
Unit Note
ns 1
ns 1,2
ns 2
ns 3
ns 3
ns 3
ns 3
ns 2
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. tSS applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time.
tSH applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time.
15.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min Typ
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
1.37
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
1.30
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
Notes : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Max
4.37
3.8
5.6
5.0
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
3
3
1,2
1,2
11 of 14
Rev. 1.0 July 2007
11 Page | ||
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