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PDF ICS1893AG Data sheet ( Hoja de datos )
| Número de pieza | ICS1893AG | |
| Descripción | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated Circuit Systems, Inc.
ICS1893AG
Document Type: Data Sheet
Document Stage: Preliminary
3.3 V 10Base-T/100Base-TX Integrated PHYceiver™
General
The ICS1893AG is a re-packaged version of the ICS1893AF
in a 56-lead TSSOP 240 mil package. The ICS1893AG is a
fully integrated, Physical Layer device (PHY) that is
compliant with both the 10Base-T and 100Base-TX
CSMA/CD Ethernet Standard, ISO/IEC 8802-3. The
ICS1893AG uses the same proven silicon as the
www.DataSheeItC4US.1c8om93AF but offers a smaller form factor solution to users
where physical package size is important.
All parametric specification and timing diagrams for the
ICS1893AF apply to the ICS1893AG. Refer to the
ICS1893AF datasheet for detailed specifications and timing.
The ICS1893AG uses the same twisted-pair transmit and
re cei v e circu its a s th e ICS 18 93 AF, an d th e s ame
recommended board layout techniques apply to the
ICS1893AG.
The ICS1893AG is intended for Node applications using the
standard MII interface to the MAC.
Features
• Single 3.3 V ±10% power supply
• Supports category 5 cables with attenuation in excess of
24dB at 100 MHz across a temperature range from 0°C to
+70°C. Industrial temperature version is also available.
• DSP-based baseline wander correction to virtually
eliminate killer packets
• Low-power, 0.35-micron CMOS (typically 400 mW)
• Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sublayers of IEEE standard
• 10Base-T and 100Base-TX IEEE 802.3 compliant
• Clock or crystal supported
• Media Independent Interface (MII) supported
• Managed or Unmanaged Applications
• 10M or 100M Half and Full Duplex Modes
• Auto-Negotiation with Next Page. Parallel detection for
Legacy products
• Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
• Loopback mode for Diagnostic Functions
• Small footprint 56-pin 240 mil TSSOP package.
ICS1893AG Block Diagram
10/100 MII
MAC
Interface
MII
Management
Interface
Interface
MUX
MII
Extended
Register
Set
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
Low-Jitter
Clock
Synthesizer
Clock
100Base-TX
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Configuration
and Status
Integrated
Switch
Auto-
Negotiation
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
Power
LEDs and PHY
Address
ICS1893AG, Rev. A 04/14/05
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
April, 2005
1 page  
ICS1893AG Data Sheet - Preliminary
Table of Contents
Table of Contents
Section
8.5
8.5.1
8.5.2
8.5.3
8.6
www.DataSheet4U.com 8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.9
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
Title
Page
Register 3: PHY Identifier Register ........................................................................ 70
OUI bits 19-24 (bits 3.15:10) .................................................................................. 70
Manufacturer's Model Number (bits 3.9:4) ............................................................. 71
Revision Number (bits 3.3:0) ................................................................................. 71
Register 4: Auto-Negotiation Register ................................................................... 72
Next Page (bit 4.15) ............................................................................................... 72
IEEE Reserved Bit (bit 4.14) .................................................................................. 72
Remote Fault (bit 4.13) .......................................................................................... 73
IEEE Reserved Bits (bits 4.12:10) ......................................................................... 73
Technology Ability Field (bits 4.9:5) ....................................................................... 74
Selector Field (Bits 4.4:0) ....................................................................................... 75
Register 5: Auto-Negotiation Link Partner Ability Register .................................... 76
Next Page (bit 5.15) ............................................................................................... 76
Acknowledge (bit 5.14) .......................................................................................... 77
Remote Fault (bit 5.13) .......................................................................................... 77
Technology Ability Field (bits 5.12:5) ..................................................................... 77
Selector Field (bits 5.4:0) ....................................................................................... 77
Register 6: Auto-Negotiation Expansion Register .................................................. 78
IEEE Reserved Bits (bits 6.15:5) ........................................................................... 78
Parallel Detection Fault (bit 6.4) ............................................................................. 79
Link Partner Next Page Able (bit 6.3) .................................................................... 79
Next Page Able (bit 6.2) ......................................................................................... 79
Page Received (bit 6.1) ......................................................................................... 79
Link Partner Auto-Negotiation Able (bit 6.0) .......................................................... 79
Register 7: Auto-Negotiation Next Page Transmit Register ................................... 80
Next Page (bit 7.15) ............................................................................................... 81
IEEE Reserved Bit (bit 7.14) .................................................................................. 81
Message Page (bit 7.13) ........................................................................................ 81
Acknowledge 2 (bit 7.12) ....................................................................................... 81
Toggle (bit 7.11) ..................................................................................................... 81
Message Code Field / Unformatted Code Field (bits 7.10:0) ................................. 81
Register 8: Auto-Negotiation Next Page Link Partner Ability Register ................... 82
Next Page (bit 8.15) ............................................................................................... 83
IEEE Reserved Bit (bit 8.14) .................................................................................. 83
Message Page (bit 8.13) ........................................................................................ 83
Acknowledge 2 (bit 8.12) ....................................................................................... 83
Message Code Field / Unformatted Code Field (bits 8.10:0) ................................. 83
ICS1893AG, Rev. A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
5
April, 2005
5 Page 
ICS1893AG Data Sheet - Preliminary
Chapter 1 Abbreviations and Acronyms
Table 1-1. Abbreviations and Acronyms (Continued)
Abbreviation /
Acronym
Interpretation
OSI Open Systems Interconnection
OUI Organizationally Unique Identifier
PCS
PHY
Physical Coding sublayer
physical-layer device
The ICS1893AG is a physical-layer device, also referred to as a ‘PHY’ or ‘PHYceiver’.
(The ICS1890 is also a physical-layer device.)
PLL
www.DataSheet4U.com PMA
phase-locked loop
Physical Medium Attachment
PMD
ppm
Physical Medium Dependent
parts per million
QFP
RO
quad flat pack
read only
R/W
R/W0
read/write
read/write zero
SC self-clearing
SF Special Functions
SFD
SI
SQE
Start-of-Frame Delimiter
Stream Interface, Serial Interface, or Symbol Interface.
With reference to the MII/SI pin, the acronym ‘SI’ has multiple meanings.
• Generically, SI means 'Stream Interface', and is documented as such in this data
sheet.
• However, when the MAC/Repeater Interface is configured for:
– 10M operations, SI is an acronym for 'Serial Interface'.
– 100M operations, SI is an acronym for 'Symbol Interface'.
Signal Quality Error
SSD
STA
Start-of-Stream Delimiter
Station Management Entity
STP
TAF
shielded twisted pair
Technology Ability Field
TP-PMD
Typ.
Twisted-Pair Physical Layer Medium Dependent
typical
UTP
unshielded twisted pair
ICS1893AG, Rev. A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
11
April, 2005
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet ICS1893AG.PDF ] | |
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