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PDF EM643FV16FU Data sheet ( Hoja de datos )

Número de pieza EM643FV16FU
Descripción 256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Fabricantes Emerging Memory & Logic Solutions 
Logotipo Emerging Memory & Logic Solutions Logotipo



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No Preview Available ! EM643FV16FU Hoja de datos, Descripción, Manual

merging Memory & Logic Solutions Inc.
Document Title
EM643FV16FU Series
Low Power, 256Kx16 SRAM
256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 Initial Draft
www.DataShe0e.t14U.com
2’nd Draft
Add Pb-free part number
Draft Date
May 26 , 2003
February 13 , 2004
Remark
Preliminary
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1

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EM643FV16FU pdf
merging Memory & Logic Solutions Inc.
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1=3070, R2=3150
www.DataShee3t4.UV.cToMm=2.8V
EM643FV16FU Series
Low Power, 256Kx16 SRAM
VTM3)
R12)
CL1)
R22)
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
55ns
Min Max
Read cycle time
tRC 55 -
Address access time
tAA - 55
Chip select to output
tCO - 55
Output enable to valid output
tOE - 25
UB, LB acess time
tBA 25
Chip select to low-Z output
tLZ 10 -
UB, LB enable to low-Z output
tBLZ
5-
Output enable to low-Z output
tOLZ
5-
Chip disable to high-Z output
tHZ 0 20
UB, LB disable to high-Z output
tBHZ
0 20
Output disable to high-Z output
tOHZ
0 20
Output hold from address change
tOH 10 -
70ns
Min Max
70 -
- 70
- 70
- 35
35
10 -
5-
5-
0 25
0 25
0 25
10 -
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
55ns
Min Max
70ns
Min Max
Write cycle time
tWC
55 -
70 -
Chip select to end of write
tCW
45 -
60 -
Address setup time
tAS
0-
0-
Address valid to end of write
tA W
45 -
60 -
UB, LB valid to end of write
tB W
45 -
60 -
Write pulse width
tW P
40 -
55 -
Write recovery time
tWR
0-
0-
Write to ouput high-Z
tWHZ
0 20 0 25
Data to write time overlap
tDW 25
30
Data hold from write time
tDH
0-
0-
End write to output low-Z
tOW
5-
5-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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EM643FV16FU arduino
merging Memory & Logic Solutions Inc.
EM643FV16FU Series
Low Power, 256Kx16 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
www.DataSheet4U2.c.omDevice Type
3. Density
4. Option
5. Technology
6. Operating Voltage
11. Power
10. Speed
9. Packages
8. Version
7. Orgainzation
1. Memory Component
2. Device Type
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
4. Mode Option
0 -------- Dual CS
1 -------- Single CS
2 -------- Multiplexed Address
3 -------- Single CS with LB,UB (tBA=tOE)
4 -------- Single CS with LB,UB (tBA=tCO)
5 -------- Dual CS with LB,UB (tBA=tOE)
6 -------- Dual CS with LB,UB (tBA=tCO)
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
6. Operating Voltage
Blank ------------------- 5V
V ------------------------- 2.7V~3.6V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
8. Version
Blank ----------------- Mother Die
A ----------------------- First revision
B ----------------------- Second revision
C ----------------------- Third revision
D ----------------------- Fourth revision
E ----------------------- Fifth revision
F ----------------------- Sixth revision
9. Package
Blank ---------------------- FPBGA
S ---------------------------- 32 sTSOP1
T ---------------------------- 32 TSOP1
U ---------------------------- 44 TSOP2
W ---------------------------- Wafer
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power (Pb-free)
L ---------------------- Low Power
S ---------------------- Standard Power
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