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PDF TDA6812-5 Data sheet ( Hoja de datos )
| Número de pieza | TDA6812-5 | |
| Descripción | TV-Stereo Processor | |
| Fabricantes | Siemens Semiconductor | |
| Logotipo |  |
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TV-Stereo Processor
Preliminary Data
TDA 6812-5
Bipolar IC
Features
www.DataSheet4qU.cHomigh quality stereo signal processing
q High S/N ratio
q I2C Bus
q Clipping detector and clock generator
q NICAM or AM sound inputs
q Volume control
q Universal audio interface for DOLBY, EQUALIZER,
SURROUND SOUND features
q Multiplex 3-SCART connections
q Independent headphones
P-DIP-40-2
Type
TDA 6812-5
Ordering Code
Q67000-A5127
Package
P-DIP-40-2
TDA 6812-5 is a complete system for stereo TV-sound, controlled on an I2C Bus. The device is
made up of three functional blocks.
1. Stereo Processing with High Quality (better than DIN 45500; suitable for NICAM and CD for
G-standard with I2C-controlled crosstalk compensation; selectable gain 0/6 dB
a) Three stereo AF-inputs
b) Random switching of all inputs to all outputs
c) Stereo SCART-interface
d) Stereo loudspeaker signal section with volume precontrol, treble/bass control, enlargement of
quasi-stereo/stereo sound base, separate L/R-volume control, equalizer interface after tone
control
e) Stereo headphones signal section with Ch1/Ch2 and volume control
2. TV-Identification-Signal Decoder
a) Active pilot-tone filter
b) Phase-independent rectifier with very narrow bandwidth for identification-signal decoding
c) Digital integrator for noise rejection
d) Multiplexer for cyclic scanning for stereo or dual-sound identification
e) Externally synchronized PLL for reference-signal generation: synchronization with line sync
pulse or 62.5-kHz clock, integrated crystal oscillator and 4-MHz crystal, or with external
4-MHz timing signal
113 06.94
1 page  
TDA 6812-5
Circuit Description
Signal Section
The dematrixing and switching of multichannel TV-sound signals are performed in the matrix and
switch section by the dual-carrier method. Crosstalk compensation is on the sound 1 input. The
compensation stage has a range of ± 3 dB with a smallest increment of 0.2 dB, and gain can also
be switched between 0 and 6 dB. In addition to the two inputs for the demodulated sound carriers,
www.DataSheett4hUe.croemare three dual-channel SCART-inputs. The two matrix AF-inputs can be bypassed internally
so that decoded stereo signals of other systems (NICAM) can also be processed. The switch
section terminates in the SCART-output and signal paths for the loudspeaker and headphones
outputs. AF-inputs can be randomly switched to AF-outputs (8-6 matrix).
In the loudpeaker signal path there is an inital volume control with a range of 0/– 15 dB and an
increment of 1.25 dB. In conjunction with the main volume control that follows the tone control, very
high overdriving immunity is ensured. The switchable quasi-stereo section that follows produces a
stereo listening effect for mono signals through a 180 oC phase shift at mid-range frequencies
(approx. 1 kHz) in one channel. The following bass control has an increment of 3 dB in its setting
range of + 15/– 12 dB. The cut-off frequency for each channel is set by an external capacitor. The
circuit for enlarging the stereo sound base can be cut in for stereo signals to make the aural
impression even more stereo-like by frequency-dependent antiphase crosstalk of 55 %. This works
with the same cut-off frequency as the bass control, but the function is largely independent. The
treble control, whose cut-off frequency is also set by an external capacitor, likewise has an
increment of 3 dB in a setting range of ± 12 dB. The main value control with maximum gain of 10
dB, which can be adjusted separately for L and R, terminates the loudspeaker signal path. 57 steps
with an increment of 1.25 dB mean a setting range of 71.25 dB. Functions like balance or loudness
are implemented by software setting of the appropriate tone and volume controls. In the tone-
control section there is a clipping detector that can be read on the I2C Bus and enables automatic
volume correction by the controller. After each reading the clipping bit is reset, which enables a
renewed check for clipping with each I2C Bus read operation.
The headphones signal path includes a volume control with joint L/R-setting. 32 increments of 2 dB
produce a range of 62 dB (31 x 2 dB = 62 dB).
Identification-Signal Decoder
The input of the identification-signal decoder consists of an operational amplifier for selectivity of
the pilot tone and its sidebands with an external LC-circuit. The signal is fed to a phase-independent
active bandpass filter of very narrow bandwidth (externally adjustable) that detects the presence of
the lower sideband of the pilot carrier modulated with the identification signal. The center frequency
of the filter is switched back and forth between dual and stereo by a multiplexer (software-controlled
timing). The multiplexer halts when a sideband is detected. This first "detected" criterion is freed
from noise by a digital integrator followed by a comparator and can then be read on the I2C Bus
(talker) as stereo or dual mode. The µC controls the signal paths. All necesssary timing signals are
derived from a fast settling PLL synchronized by a reference frequency. This reference must be
sufficiently identical to the horizontal frequency, but no phase locking is necessary. This means
that it is possible to use the crystal-controlled frequency of 62.5 kHz that is often found in PLL-tuning
systems. As further alternatives there is an integrated crystal oscillator that requires a 4-MHz
crystal, or it is possible to use a clock frequency of 1 or 4 MHz.
Semiconductor Group
117
5 Page 
TDA 6812-5
Absolute Maximum Ratings
TA = 0 to 70 oC; all voltages relatives to VSS
Parameter
Symbol Limit Values
min. max.
Supply voltage
www.DataSheeMt4Ua.cxo.mDC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-voltage
Max. DC-current
Max. DC-current
Max. DC-current
Max. DC-current
Max. DC-current
Max. DC-current
Max. DC-current
Max. DC-current
Max. DC-current
Max. DC-current
Max. DC-current
ESD-voltage
V21
V1
V2
V3
V5
V7
V8
V9
V10
V11
V12
V15
V16
V17
V18
V19
V20
V24
V25
V28
V29
V33
V34
V36
V38
I6
I13
I14
I21
I22
I26
I27
I30
I31
I35
I39
VESD
0 14
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
0 V32
02
02
02
02
02
02
02
02
02
02
02
–2 2
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
kV
Remarks
HBM (R = 1.5 kΩ,
C = 100 pF)
Semiconductor Group
123
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA6812-5.PDF ] | |
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