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PDF LH28F640BF Data sheet ( Hoja de datos )
| Número de pieza | LH28F640BF | |
| Descripción | (LH28FxxxBF) Page Mode Dual Work Flash Memory | |
| Fabricantes | Sharp | |
| Logotipo |  |
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APPENDIX No. F U M 0 0 7 0 1
ISSUE:
Jan. 8, 2003
Page Mode Dual Work Flash Memory
32M-bit, 64M-bit, 128M-bit
LH28F320BF, LH28F640BF, LH28F128BF Series
Appendix
Rev. F
1 page  
FUM00701
3
During dual work operation, read operations to the
partition being erased or programmed access the status
register which indicates whether the erase or program
operation is successfully completed or not. Dual work
operation cannot be executed during full chip erase and
OTP program mode.
Memory array data can be read in asynchronous 8-word
page mode. The default after power-up or device reset is
the asynchronous read mode in which 8-word page mode
is available.
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The product contains a page buffer of 16 words. In the
page buffer program mode, the data to be programmed is
first stored into the page buffer before being transferred to
the memory array. A page buffer program has high speed
program performance. The page buffer program operation
programs up to 16-word data at sequential addresses
within one block. That is, this operation cannot be used to
program data at addresses separated by something even in
the same block, or divided into different blocks. Page
buffer program cannot be applied to OTP block described
later in this section.
For the parameter blocks and main blocks, individual
block locking scheme that allows any block to be locked,
unlocked or locked-down with no latency. The time
required for block locking is less than the minimum
command cycle time (minimum time from the rising edge
of CE# or WE# to write the command to the next rising
edge of CE# or WE#). The block is locked via the Set
Block Lock Bit command or Set Block Lock-down bit
command. Block erase, full chip erase and (page buffer)
program operation cannot be executed for locked block,
to protect codes and data from unwanted operation due to
noises, etc. When the WP# pin is at VIL, the locked-down
block cannot be unlocked. When WP# pin is at VIH, lock-
down bits are disabled and any block can be locked or
unlocked through software. After WP# goes VIL, any
block previously marked lock-down revert to that state.
At power-up or device reset, all blocks default to locked
state and are not locked-down, regardless of the states
before power-off or reset operation. This means that all
write operations on any block are disabled.
Unauthorized use of cellular phone, communication
device, etc. can be avoided by storing a security code into
the 8-word OTP (One Time Program) block (see Figure
4) provided in addition to the parameter and main blocks.
To ensure high reliability, a lock function for the OTP
block is provided.
The product has a VPP pin which monitors the level of the
power supply voltage. When VPP ≤ VPPLK, memory
contents cannot be altered and the data in all blocks are
completely write protected (see Note 1). Note that the VPP is
used only for checking the supply voltage, not used for
device power supply pin.
Automatic Power Savings (APS) is the low power
features to help increase battery life in portable
applications. APS mode is initiated shortly after read
cycle completion. In this mode, its current consumption
decreases to the value equivalent of that in the standby
mode. Standard address access timings (tAVQV) provide
new data when addresses are changed. During dual work
operation (one partition being erased or programmed,
while other partitions are read modes), the device cannot
enter the Automatic Power savings mode if the input
address remains unchanged.
A CUI (Command User Interface) serves as the interface
between the system processor and internal operation of
the device. A valid command sequence written to the CUI
initiates device automation. The product uses an
advanced WSM (Write State Machine) to automatically
execute erase and program operations within the memory
array. The WSM is controlled through the CUI. By
writing a valid command sequence to the CUI, the WSM
is instructed to automatically handle the sequence of
internal events and timings required to block erase, full
chip erase, (page buffer) program or OTP program
operations.
Status registers are prepared for each partition to indicate
the status of the partition. Even if the WSM is occupied
by executing erase or program operation in one partition,
the status register of other partition reports that the device
is not busy when the device is set to 2, 3 or 4 partitions
configuration.
(Note 1) Please note following:
• For the lockout voltage VPPLK to inhibit all write
functions, refer to specifications.
• VPP should be kept lower than VPPLK (GND) during
read operations to protect the data in all blocks.
Rev. 2.44
5 Page 
FUM00701
9
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BLOCK NUMBER ADDRESS RANGE
70 32K-WORD
1F8000H - 1FFFFFH
69 32K-WORD
1F0000H - 1F7FFFH
68 32K-WORD
1E8000H - 1EFFFFH
67 32K-WORD
1E0000H - 1E7FFFH
66 32K-WORD
1D8000H - 1DFFFFH
65 32K-WORD
1D0000H - 1D7FFFH
64 32K-WORD
1C8000H - 1CFFFFH
63 32K-WORD
1C0000H - 1C7FFFH
62 32K-WORD
1B8000H - 1BFFFFH
61 32K-WORD
1B0000H - 1B7FFFH
60 32K-WORD
1A8000H - 1AFFFFH
59 32K-WORD
1A0000H - 1A7FFFH
58 32K-WORD
198000H - 19FFFFH
57 32K-WORD
190000H - 197FFFH
56 32K-WORD
188000H - 18FFFFH
55 32K-WORD
180000H - 187FFFH
54 32K-WORD
53 32K-WORD
52 32K-WORD
51 32K-WORD
50 32K-WORD
49 32K-WORD
48 32K-WORD
47 32K-WORD
46 32K-WORD
45 32K-WORD
44 32K-WORD
43 32K-WORD
42 32K-WORD
41 32K-WORD
40 32K-WORD
39 32K-WORD
178000H - 17FFFFH
170000H - 177FFFH
168000H - 16FFFFH
160000H - 167FFFH
158000H - 15FFFFH
150000H - 157FFFH
148000H - 14FFFFH
140000H - 147FFFH
138000H - 13FFFFH
130000H - 137FFFH
128000H - 12FFFFH
120000H - 127FFFH
118000H - 11FFFFH
110000H - 117FFFH
108000H - 10FFFFH
100000H - 107FFFH
BLOCK NUMBER ADDRESS RANGE
38 32K-WORD
0F8000H - 0FFFFFH
37 32K-WORD
0F0000H - 0F7FFFH
36 32K-WORD
0E8000H - 0EFFFFH
35 32K-WORD
0E0000H - 0E7FFFH
34 32K-WORD
0D8000H - 0DFFFFH
33 32K-WORD
0D0000H - 0D7FFFH
32 32K-WORD
0C8000H - 0CFFFFH
31 32K-WORD
0C0000H - 0C7FFFH
30 32K-WORD
0B8000H - 0BFFFFH
29 32K-WORD
0B0000H - 0B7FFFH
28 32K-WORD
0A8000H - 0AFFFFH
27 32K-WORD
0A0000H - 0A7FFFH
26 32K-WORD
098000H - 09FFFFH
25 32K-WORD
090000H - 097FFFH
24 32K-WORD
088000H - 08FFFFH
23 32K-WORD
080000H - 087FFFH
22 32K-WORD
21 32K-WORD
20 32K-WORD
19 32K-WORD
18 32K-WORD
17 32K-WORD
16 32K-WORD
15 32K-WORD
14 32K-WORD
13 32K-WORD
12 32K-WORD
11 32K-WORD
10 32K-WORD
9 32K-WORD
8 32K-WORD
7 4K-WORD
6 4K-WORD
5 4K-WORD
4 4K-WORD
3 4K-WORD
2 4K-WORD
1 4K-WORD
0 4K-WORD
078000H - 07FFFFH
070000H - 077FFFH
068000H - 06FFFFH
060000H - 067FFFH
058000H - 05FFFFH
050000H - 057FFFH
048000H - 04FFFFH
040000H - 047FFFH
038000H - 03FFFFH
030000H - 037FFFH
028000H - 02FFFFH
020000H - 027FFFH
018000H - 01FFFFH
010000H - 017FFFH
008000H - 00FFFFH
007000H - 007FFFH
006000H - 006FFFH
005000H - 005FFFH
004000H - 004FFFH
003000H - 003FFFH
002000H - 002FFFH
001000H - 001FFFH
000000H - 000FFFH
Figure 2.2. Memory Map for 32Mbit (Bottom Parameter)
Rev. 2.44
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