TDAT162G52 Datasheet PDF - Agere Systems
| Part Number | TDAT162G52 | |
| Description | SONET/SDH 155/622/2488 Mbits/s Data Interface | |
| Manufacturers | Agere Systems | |
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Data Sheet
August 18, 2004
MARS®2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Features
■ One of the next-generation, system-on-a-chip
devices of Agere Systems’ multiservice access &
rate solutions MARSTM family of framers.
www.DataSheet4U.com
■
Transmission convergence and SONET/SDH ter-
minal functionality for linear networks.
■ Versatile IC supports 155/622/2488 Mbits/s
SONET/SDH interface solutions for packet over
SONET (POS), packet over fiber (POF), or asyn-
chronous transfer mode (ATM) applications.
■ Low-power 1.6 V/3.3 V operation.
SONET/SDH Interface
■ Termination of quad STS-3/STM-1,
quad STS-12/STM-4, or single STS-48/STM-16.
■ Supports overhead processing for transport and
path overhead bytes.
■ Optional insertion and extraction of overhead bytes
via serial overhead interface.
■ STS pointer processing to align the receive frame
to the system frame.
■ Support for 1 + 1 and 1:1 linear networks.
■ Full path termination and SPE extraction/insertion.
■ SONET/SDH compliant condition and alarm
reporting.
■ Handles all concatenation levels of STS-3c to
STS-48c (in multiples of 3: e.g., 3c, 6c, 9c, etc.).
■ Built-in diagnostic loopback modes.
■ Compliant with the following Telcordia Technolo-
gies®, ANSI®, and ITU standards:
— GR-253 CORE: SONET Transport Systems:
Common Generic Criteria.
— ITU-T G.707: Network Node Interface for the
Synchronous Digital Hierarchy.
— ITU-T G.803: Architecture of Transport Net-
works Based on the Synchronous Digital Hierar-
chy.
— T1.105: SONET-Basic Description including
Multiplex Structure, Rates, and Formats.
— T1.105.02 SONET-Payload Mappings.
— T1.105.03 SONET-Jitter at Network Interfaces.
— T1.105.06 SONET Physical Layer Specifica-
tions.
— T1.105.07 SONET-Sub-STS-1 Interface Rates
and Formats Specification.
— ITU-T I.432: B-ISDN User-Network Interface-
Physical Layer Specification.
— IETF RFC 2615: PPP over SONET/SDH.
— IETF RFC 1661: The Point-to-Point Protocol
(PPP).
— IETF RFC 1662: PPP in HDLC-like Framing.
Data Processing
■ Provisionable data engine supports payload inser-
tion/extraction for PPP, ATM, or HDLC streams.
■ Extraction and insertion of DS3 frames containing
HDLC or ATM data streams for up to 16 channels.
■ Integrated UTOPIA Level 2 and Level 3 compatible
physical layer interface for packets or ATM cells.
■ Provides/supports internal E3 mapping.
■ Supports DS3/PLCP and clear channel DS3 map-
ping.
■ Insertion and extraction of up to 16 separate data
channels.
■ Direct cell/packet over fiber interface device.
■ Compliant with ATM forum, ITU standards, and
IETF standards.
■ Supports generic framing procedure (GFP) proto-
col.
Interfaces
■ Enhanced UTOPIA interface for cell and packet
transfer.
■ IEEE® 1149.1 port with BIST, scan, and boundry
scan.
Microprocessor Interface
■ Up to 66 MHz synchronous.
■ 16-bit address and 16-bit data interface.
■ Synchronous or asynchronous modes available.
■ Configurable to operate with most commercial
microprocessors.
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Figures
Figure
Page
Figure 1. MARS2G5 P-Pro Block Diagram ............................................................................................................ 27
Figure 2. GFP Relationship to Transport Payloads ............................................................................................... 28
Figure 3. MARS2G5 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 29
Figure 4. MARS1G2 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 30
Figure 5. MARS622 P-Pro Device Interface Speed/Rate Diagram ....................................................................... 31
Figure 6. MARS2G5 P-Pro External Interfaces ..................................................................................................... 33
Figure 7. Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode ................................................................ 34
Figure 8. Clock Domains in the Packet-Over-Fiber (POF) Mode .......................................................................... 35
Figure 9. PLL Outputs Lock-In Process ............................................................................................................... 122
www.DataSheet4U.cFoimgure 10. Microprocessor Interface Synchronous Write Cycle (MPU_MPMODE (Pin D8) = 1) ......................... 125
Figure 11. Microprocessor Interface Synchronous Read Cycle (MPU_MPMODE (Pin D8) = 1) ........................ 127
Figure 12. Microprocessor Interface Asynchronous Write Cycle Description (MPU_MPMODE (Pin D8) = 0) .... 129
Figure 13. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) ................................. 131
Figure 14. PM Reset Signal Generation .............................................................................................................. 159
Figure 15. General Input/Output (GPIO) ............................................................................................................. 161
Figure 16. Interrupt Functionality ......................................................................................................................... 162
Figure 17. Loopback Operation ........................................................................................................................... 163
Figure 18. MARS2G5 P-Pro Block Diagram Indicating the Signal Pins per Block .............................................. 175
Figure 19. Line Interface ...................................................................................................................................... 177
Figure 20. LVPECL Load Connections ................................................................................................................ 179
Figure 21. Receive Line-Side Timing Waveform ................................................................................................. 180
Figure 22. Transmit Line-Side Timing Waveform—OC-48 Contraclocking ......................................................... 181
Figure 23. Transmit Line-Side Timing Waveform—OC-48 Forward Clocking ..................................................... 181
Figure 24. Transmit Line-Side Timing Waveform—Frame Sync ......................................................................... 181
Figure 25. High-Level Block Interconnect ............................................................................................................ 184
Figure 26. TOHP-48 Block Diagram (One Channel) ........................................................................................... 185
Figure 27. Time-Slot Assignments ...................................................................................................................... 194
Figure 28. REI-L (MS-REI) Location .................................................................................................................... 202
Figure 29. RTOH Interface .................................................................................................................................. 205
Figure 30. TTOH Interface ................................................................................................................................... 205
Figure 31. STS-3/STM1, STS-12/STM-4, and STS-48/STM-16 Transmit TOAC Interface Timing ..................... 206
Figure 32. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing .............................................. 206
Figure 33. STS-3/STM-1 Receive TOAC Interface Timing .................................................................................. 207
Figure 34. Signal Degrade and Failure Parameters for BER .............................................................................. 228
Figure 35. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of Pointer Processor ........................ 250
Figure 36. Top Level Block Diagram of the Pointer Processor Block .................................................................. 251
Figure 37. Overview of Pointer Processor Register Map .................................................................................... 257
Figure 38. Path Terminator Block Diagram ......................................................................................................... 345
Figure 39. Block Diagram of SPE Mapper Block ................................................................................................. 346
Figure 40. Direct Mapping into STS SPE ............................................................................................................ 349
Figure 41. STS-Nc SPE ....................................................................................................................................... 349
Figure 42. Asynchronous Mapping of DS3 into STS-1 SPE ................................................................................ 350
Figure 43. Asynchronous Mapping of E3 into STS-1 SPE .................................................................................. 351
Figure 44. STS-48 Frame Structure .................................................................................................................... 352
Figure 45. STS-12 Frame Structure .................................................................................................................... 353
Figure 46. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of STS Receive Terminator ............. 391
Figure 47. STS Receive Terminator (RXT) Functional Block Diagram ............................................................... 392
Figure 48. Interpreter State Machine ................................................................................................................... 394
Figure 49. STS-12 RXT Concatenated Offset Passing ....................................................................................... 398
Figure 50. STS-6 RXT Concatenated Offset Passing ......................................................................................... 398
Figure 51. STS-3 and STS-1 RXT Concatenated Offset Passing ....................................................................... 399
Agere Systems Inc.
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