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PDF 24L04F-W Data sheet ( Hoja de datos )
| Número de pieza | 24L04F-W | |
| Descripción | BR24L04F-W | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Memory ICs
BR24L04-W / BR24L04F-W / BR24L04FJ-W
BR24L04FV-W / BR24L04FVM-W
512×8 bit electrically erasable PROM
BR24L04-W / BR24L04F-W / BR24L04FJ-W /
BR24L04FV-W / BR24L04FVM-W
The BR24L04-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable.
www.DataSheet4U.com
∗ I2C BUS is a registered trademark of Philips.
zApplications
General purpose
zFeatures
1) 512 registers × 8 bits serial architecture.
2) Single power supply (1.8V to 5.5V).
3) Two wire serial interface.
4) Self-timed write cycle with automatic erase.
5) 16byte Page Write mode.
6) Low power consumption.
Write (5V) : 1.2mA (Typ.)
Read (5V) : 0.2mA (Typ.)
Standby (5V) : 0.1µA (Typ.)
7) DATA security
Write protect feature (WP pin).
Inhibit to WRITE at low VCC.
8) Small package - - - DIP8 / SOP8 / SOP-J8 / SSOP-B8 / MSOP-8
9) High reliability EEPROM with Double-Cell structure
10) High reliability fine pattern CMOS technology.
11) Endurance : 1,000,000 erase / write cycles
12) Data retention : 40 years
13) Filtered inputs in SCL•SDA for noise suppression.
14) Initial data FFh in all address.
zAbsolute maximum ratings (Ta=25°C)
Parameter
Symbol
Limits
Supply voltage
VCC −0.3 to +6.5
800(DIP8) ∗1
450(SOP8) ∗2
Power dissipation
Pd 450(SOP-J8) ∗2
300(SSOP-B8) ∗3
310(MSOP8) ∗4
Storage temperature
Tstg
−65 to +125
Operating temperature
Topr
−40 to +85
Terminal voltage
− −0.3 to VCC+0.3
∗1 Reduced by 8.0mW for each increase in Ta of 1°C over 25°C.
∗2 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C.
∗3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
∗4 Reduced by 3.1mW for each increase in Ta of 1°C over 25°C.
Unit
V
mW
°C
°C
V
1/25
1 page  
Memory ICs
BR24L04-W / BR24L04F-W / BR24L04FJ-W
BR24L04FV-W / BR24L04FVM-W
zAC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V)
Parameter
Clock frequency
Data clock "HIGH" period
Data clock "LOW" period
SDA and SCL rise time ∗1
www.DataSheet4U.com SDA and SCL fall time ∗1
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus free time
Write cycle time
Noise spike width (SDA and SCL)
WP hold time
WP setup time
WP high period
Symbol
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tl
tHD:WP
tSU:WP
tHIGH:WP
Fast-mode
2.5V ≤ Vcc ≤ 5.5V
Min. Typ. Max.
− − 400
0.6 −
−
1.2 −
−
− − 0.3
− − 0.3
0.6 −
−
0.6 −
−
0−−
100 −
−
0.1 − 0.9
0.1 −
−
0.6 −
−
1.2 −
−
−−5
− − 0.1
0−−
0.1 −
−
1.0 −
−
Standard-mode
1.8V ≤ Vcc ≤ 5.5V
Min. Typ. Max.
− − 100
4.0 −
−
4.7 −
−
− − 1.0
− − 0.3
4.0 −
−
4.7 −
−
0−−
250 −
−
0.2 − 3.5
0.2 −
−
4.7 −
−
4.7 −
−
−−5
− − 0.1
0−−
0.1 −
−
1.0 −
−
∗1 Not 100% tested.
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
ns
µs
µs
5/25
5 Page 
Memory ICs
BR24L04-W / BR24L04F-W / BR24L04FJ-W
BR24L04FV-W / BR24L04FVM-W
zCurrent read
www.DataSheet4U.com
S
TR
AE
R SLAVE A
T ADDRESS D
SDA
LINE
1 0 1 0 A2 A1 PS
D7
DATA
S
T
O
P
D0
RA
/C
WK
Fig.10 CURRENT READ CYCLE TIMING
A
C
K
• In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the
internal address counter is increased by one from the last accessed address (n).
Thus Current Read outputs the data of the next word address (n+1).
If the last command is Byte or Page Write, the internal address counter stays at the last address (n).
Thus Current Read outputs the data of the word address (n).
• If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue
to transmit the data. [ It can transmit all data (4kbit 512word) ]
• If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
zRandom read
S
T
A
R
T
SLAVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS(n)
S
TR
AE
R SLAVE A
T ADDRESS D
DATA(n)
S
T
O
P
SDA
LINE
1 0 1 0 A2A1PS
WA
7
WA
0
1 0 1 0 A2A1PS
D7
D0
RA A RA A
/C C /C C
WK K WK K
Fig.11 RANDOM READ CYCLE TIMING
• Random read operation allows the master to access any memory location indicated word address.
• If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue to
transmit the data. [ It can transmit all data (4kbit 512word) ]
• If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
11/25
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 24L04F-W.PDF ] | |
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