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PDF W3DG6418V-AD1 Data sheet ( Hoja de datos )
| Número de pieza | W3DG6418V-AD1 | |
| Descripción | SDRAM UNBUFFERED | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs
W3DG6418V-AD1
PRELIMINARY*
128MB - 16Mx64 SDRAM UNBUFFERED
FEATURES
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V ± 0.3V Power Supply
144 pin SO-DIMM
DESCRIPTION
The W3DG6418V is a 16Mx64 synchronous DRAM module
which consists of eight 16Mx8 SDRAM components
in TSOP II package, and one 2Kb EEPROM in an 8
pin TSSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
www.DataSheet4U.com
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT
PIN FRONT PIN BACK PIN FRONT PIN BACK PIN BACK PIN
1 VSS 2 VSS 49 DQ13 50 DQ45 97 DQ22 98
3 DQ0 4 DQ32 51 DQ14 52 DQ46 99 DQ23 100
5 DQ1 6 DQ33 53 DQ15 54 DQ47 101 VCC 102
7 DQ2 8 DQ34 55 VSS 56 VSS 103 A6 104
9 DQ3 10 DQ35 57 NC 58 NC 105 A8 106
11 VCC 12 VCC 59 NC 60 NC 107 VSS 108
13 DQ4 14 DQ36 61 CK0 62 CKE0 109 A9 110
15 DQ5 16 DQ37 63 VCC 64 VCC 111 A10/AP 112
17 DQ6 18 DQ38 65 RAS# 66 CAS# 113 VCC 114
19 DQ7 20 DQ39 67 WE# 68 NC 115 DQM2 116
21 VSS 22 VSS 69
23 DQM0 24 DQM4 71
25 DQM1 26 DQM5 73
CS0#
NC
NC
70
72
74
NC 117 DQM3 118
NC 119 VSS 120
CK1 121 DQ24 122
27 VCC 28 VCC 75 VSS 76 VSS 123 DQ25 124
29 A0 30 A3 77 NC 78 NC 125 DQ26 126
31 A1 32 A4 79 NC 80 NC 127 DQ27 128
33 A2 34 A5 81 VCC 82 VCC 129 VCC 130
35 VSS 36 VSS 83 DQ16 84 DQ48 131 DQ28 132
37 DQ8 38 DQ40 85 DQ17 86 DQ49 133 DQ29 134
39 DQ9 40 DQ41 87 DQ18 88 DQ50 135 DQ30 136
41 DQ10 42 DQ42 89 DQ19 90 DQ51 137 DQ31 138
43 DQ11 44 DQ43 91 VSS 92 VSS 139 VSS 140
45 VCC 46 VCC 93 DQ20 94 DQ52 141 **SDA 142
47 DQ12 48 DQ44 95 DQ21 96 DQ53 143 VCC 144
BACK
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQM6
DQM7
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
PIN NAMES
A0 – A11 Address Input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CK0, CK1 Clock Input
CKE0
Clock Enable Input
CS0#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE# Write Enable
DQM0-7 DQM
VCC Power Supply (3.3V)
VSS Ground
SDA Serial Data I/O
SCL Serial Clock
DNU Do Not Use
NC No Connect
** These pins should be NC in the system which
does not support SPD.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October 2004
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3DG6418V-AD1
PRELIMINARY
AC TIMING PARAMETERS
Speed Grade
100MHz
Symbol
tCK
tCH
tCL
tIS
Parameter
Clock Period
Clock High Time Rated @1.5V
Clock Low Time
Input Setup Times
Address/ Command & CKE
Data
Min
10
3
3
2
2
Max
tIH Input Hold Times
Address/Command & CKE
Data
tAC Output Valid From Clock
CAS# Latency = 2 or 3,
LVTTL levels, Rated @ 50
pF all outputs switching
tOH Output Hold From Clock Rated @ 50 pF (1.8 ns @ 0 pf)
tOHZ Output Valid to Z
www.DatCtCaDSheCeASt4toUC.AcSoDmelay
tCBD CAS Bank Delay
tCKE CKE to Clock Disable
tRP RAS Precharge Time
tRAS RAS Active Time
tRCD Activate to Command Delay (RAS to CAS Delay)
tRRD RAS to RAS Bank Activate Delay
tRC RAS Cycle Time
tDQD DQM to Input Data Delay
tDWD Write Cmd. to Input Data Delay
tMRD Mode Register set to Active delay
tROH Precharge to O/P in High Z
tDQZ DQM to Data in High Z for read
tDQM DQM to Data mask for write
tDPL Data-in to PRE Command Period
tDAL Data-in to ACT (PRE) Command period (Auto precharge)
tSB Power Down Mode Entry
tSRX Self Refresh Exit Time
tPDE Power Down Exit Set up Time
tCKSTP Clock Stop During Self Refresh or Power Down
tREF Refresh Period
tRFC Row Refresh Cycle Time
1
1
6.0
(tco = 5.2)
3
39
1
1
1
20
50
20
20
70
0
0
3
CL
2
0
20
5
1
10
1
200
64
80.0
1. Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load.
2. CL = CAS Latency
3. Data Masked on the same clock
4. Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC.
5. Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle.
6. If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high.
Speed Grade
133MHz
Min Max
7.5
2.5
2.5
1.5
1.5
0.8
0.8
5.4
(tco = 4.6)
Units
ns
ns
ns
ns
ns
ns
ns
ns
2.7
2.7 7
1
1
1
20
45
20
15
67.5
0
0
3
CL
2
0
15
5
1
10
1
200
64
75.0
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
tCK
tCK
ns
tCK
tCK
ms
ns
Notes
1
2
3
4
5
6
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October 2004
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page | ||
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