PDF 79RC32334 Data sheet ( Hoja de datos )

Número de pieza	79RC32334
Descripción	IDT Interprise Integrated Communications Processor
Fabricantes	Integrated Device Technology
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No Preview Available ! IDTTM InterpriseTM Integrated Communications Processor 79RC32334—Rev. Y Features ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture (ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions www.DataSheet4–U.cSomupports big or little endian operation – MMU with 32 page TLB – 8kB Instruction Cache, 2-way set associative – 2kB Data Cache, 2-way set associative – Cache locking per line – Programmable on a page basis to implement a write-through no write allocate, write-through write allocate, or write-back algorithms for cache management – Compatible with a wide variety of operating systems ◆ Local Bus Interface – Up to 75 MHz operation – 26-bit address bus – 32-bit data bus – Direct control of local memory and peripherals – Programmable system watch-dog timers – Big or little endian support ◆ Interrupt Controller simplifies exception management ◆ Four general purpose 32-bit timer/counters Block Diagram ◆ Programmable I/O (PIO) – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported – Implements full, direct control of discrete, SODIMM, or DIMM memories – Supports 16Mb through 512Mb SDRAM device depths – Automatic refresh generation ◆ Serial Peripheral Interface (SPI) master mode interface ◆ UART Interface – Two 16550 compatible UARTs – Baud rate support up to 1.5 Mb/s – Modem control signals available on one channel ◆ Memory & Peripheral Controller – 6 banks, up to 64MB per bank – Supports 8-,16-, and 32-bit interfaces – Supports Flash ROM, SRAM, dual-port memory, and peripheral devices – Supports external wait-state generation – 8-bit boot PROM support – Flexible I/O timing protocols EJTAG In-Circuit Emulator Interface RISCore32300 RC5000 Enhanced MIPS-II ISA Compatible Integer CPU CP0 32-page TLB 2kB 2-set, Lockable Data Cache 8kB 2-set Lockable Instr. Cache IPBus Bridge Interrupt Control 32-bit Timers DMA Control Dual UART IDT Peripheral Bus Programmable I/O SPI Control Local Memory/IO Control SDRAM Control PCI Bridge Figure 1 RC32334 Block Diagram Note: This data sheet does not apply to revision Z silicon. Contact your IDT sales representative for information on revision Z. © 2004 Integrated Device Technology, Inc. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 of 30 August 31, 2004 DSC 5701 1 page IDT 79RC32334—Rev. Y Pin Description Table The following table lists the pins provided on the RC32334. Note that those pin names followed by ”_n” are active-low signals. All external pull-ups and pull-downs require 10 kΩ resistor. Name Reset Drive Type State Strength Status Capability Description Local System Interface mem_data[31:0] I/O Z High Local System Data Bus Primary data bus for memory. I/O and SDRAM. mem_addr[25:2] www.DataSheet4U.com I/O [25:10] Z [25:17] Low Memory Address Bus These signals provide the Memory or DRAM address, during a Memory or DRAM bus transaction. During [9:2] L [16:2] High each word data, the address increments either in linear or sub-block ordering, depending on the transac- tion type. The table below indicates how the memory write enable signals are used to address discreet memory port width types. Port Width Pin Signals mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] DMA (32-bit) mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 16-bit Byte High Write Enable mem_addr[1] Not Used (Driven Byte Low Write Low) Enable 8-bit Not Used (Driven High) mem_addr[1] mem_addr[0] Byte Write Enable mem_cs_n[5:0] Output H mem_oe_n Output H Low with internal pull-up High mem_addr[22] Alternate function: reset_boot_mode[1]. mem_addr[21] Alternate function: reset_boot_mode[0]. mem_addr[20] Alternate function: reset_pci_host_mode. mem_addr[19] Alternate function: modebit [9]. mem_addr[18] Alternate function: modebit [8]. mem_addr[17] Alternate function: modebit [7]. mem_addr[16] Alternate function: sdram_addr[16]. mem_addr[15] Alternate function: sdram_addr[15]. mem_addr[14] Alternate function: sdram_addr[14]. mem_addr[13] Alternate function: sdram_addr[13]. mem_addr[11] Alternate function: sdram_addr[11]. mem_addr[10] Alternate function: sdram_addr[10]. mem_addr[9] Alternate function: sdram_addr[9]. mem_addr[8] Alternate function: sdram_addr[8]. mem_addr[7] Alternate function: sdram_addr[7]. mem_addr[6] Alternate function: sdram_addr[6]. mem_addr[5] Alternate function: sdram_addr[5]. mem_addr[4] Alternate function: sdram_addr[4]. mem_addr[3] Alternate function: sdram_addr[3]. mem_addr[2] Alternate function: sdram_addr[2]. Memory Chip Select Negated Recommend external pull-up. Signals that a Memory Bank is actively selected. Memory Output Enable Negated Recommend external pull-up. Signals that a Memory Bank can output its data lines onto the cpu_ad bus. Table 1 Pin Description (Part 1 of 7) 5 of 30 August 31, 2004 5 Page IDT 79RC32334—Rev. Y Name Reset Drive Type State Strength Status Capability Description Debug Signals debug_cpu_dma_n I/O Z debug_cpu_ack_n I/O Z www.DataShdeebeut4gU_c.cpoum_ads_n I/O Z debug_cpu_i_d_n I/O Z Low Debug CPU versus DMA Negated De-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transac- tion was generated from the CPU. Assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from DMA. Alternate function: modebit[6]. Low Debug CPU Acknowledge Negated Indicates either a data acknowledge to the CPU or DMA. Alternate function: modebit[4]. Low Debug CPU Address/Data Strobe Negated Assertion indicates that either a CPU or a DMA transaction is beginning and that the mem_data[31:4] bus has the current block address. Alternate function: modebit[5]. Low Debug CPU Instruction versus Data Negated Assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a CPU or DMA data transaction. De-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a CPU instruction transaction. Alternate function: modebit[3]. Table 1 Pin Description (Part 7 of 7) Mode Bit Settings to Configure Controller on Reset The following table lists the mode bit settings to configure the controller on cold reset. Pin ejtag_pcst[2:0] debug_cpu_i_d_n debug_cpu_ack_n debug_cpu_ads_n debug_cpu_dma_n mem_addr[17] Mode Bit Description Value 2:0 MSB (2) Clock Multiplier MasterClock is multiplied internally to gener- ate PClock 0 1 2 3 4 5 6 7 3 EndBit 0 1 4 Reserved 0 5 Reserved 0 6 TmrIntEn 0 Enables/Disables the timer interrupt on Int*[5] 1 7 Reserved for future use 1 Table 2 Boot-Mode Configuration Settings (Part 1 of 2) Mode Setting Multiply by 2 Multiply by 3 Multiply by 4 Reserved Reserved Reserved Reserved Reserved Little-endian ordering Big-endian ordering Enables timer interrupt Disables timer interrupt 11 of 30 August 31, 2004 11 Page

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