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PDF IDT74LVCH16374A Data sheet ( Hoja de datos )
| Número de pieza | IDT74LVCH16374A | |
| Descripción | 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74LVCH16374A
3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP
INDUSTRIALTEMPERATURERANGE
3.3V CMOS 16-BIT
IDT74LVCH16374A
EDGE-TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS,
5V TOLERANT I/O AND BUS-HOLD
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
www.Data•ShAelelt4inUp.cuotsm, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION
The LVCH16374A 16-bit edge-triggered D-type register is built using
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The Output Enable (OE) and clock (CLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise margin.
All pins of the LVCH16374A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/5V
supply system.
The LVCH16374A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16374A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1OE 1
48
1CLK
47
1D1
C1
1D
2OE
24
2CLK
25
2
1Q1
2D1 36
C1
1D
13 2Q1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 1999 Integrated Device Technology, Inc.
1
MARCH 1999
DSC-4643/2
1 page  
IDT74LVCH16374A
3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
tPHL
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
Propagation Delay
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
LVC Link
www.DataSheet4U.com
VIN
Pulse (1, 2)
Generator
VCC
VOUT
D.U.T.
500Ω
VLOAD
Open
GND
RT
500Ω
CL
Test Circuit for All Outputs
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
VLOAD/2
VT
tPHZ
VT
0V
VIH
VT
0V
VLOAD/2
VLZ
VOL
VOH
VHZ
0V
LVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
tSU tH
tREM
SYNCHRONOUS
CONTROL
tSU tH
Set-up, Hold, and Release Times
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
Pulse Width
VT
VT
LVC Link
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74LVCH16374A.PDF ] | |
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