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PDF IDT74LVCH16260A Data sheet ( Hoja de datos )
| Número de pieza | IDT74LVCH16260A | |
| Descripción | 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3V CMOS 12-BIT
TRI-PORT BUS EXCHANGER
WITH 5 VOLT TOLERANT I/O
AND BUS-HOLD
IDT74LVCH16260A
FEATURES:
– Typical tSK(0) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
www.DataSh–eet4EUx.tceonmded commercial range of -40°C to +85°C
– VCC = 3.3V ±0.3V, Normal Range
– VCC = 2.7V to 3.6V, Extended Range
– CMOS power levels (0.4µ W typ. static)
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVCH16260A:
– High Output Drivers: ±24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
The LVCH16260A tri-port bus exchanger is built using advanced dual
metal CMOS technology. The LVCH16260A is a high-speed 12-bit latched
bus multiplexer/transceiver for use in high-speed microprocessor applica-
tions. This bus exchanger supports memory interleaving with latched out-
puts on the B ports and address multiplexing with latched inputs on the B
ports.
The LVCH16260A tri-port bus exchanger has three 12-bit ports. Data
may be transferred between the A port and either/both of the B ports. The
latch enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage.
When a latch-enable input is high, the latch is transparent. When a latch-
enable input is low, the data at the input is latched and remains latched until
the latch enable input is returned high. Independent output enables (OE1B
and OE2B) allow reading from one port while writing to the other port.
All pins of the 12-bit Bus Exchanger can be driven from either 3.3V or
5V devices. This feature allows the use of the device as a translator in a
mixed 3.3V/5V supply system.
The LVCH16260A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16260A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
Functional Block Diagram
OE1B 29
30
LEA1B
A-1B
LATCH
12
1B1:12
LE1B
2
12
SEL
OEA
28
1
A1:12
1B-A
LATCH
12
1
M
12 U
X
0
12
27
LE2B
12
12
2B-A
LATCH
12
55
LEA2B
56
OE2B
A-2B
LATCH
12
EXTENDED COMMERCIAL TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
1
2B1:12
MARCH 1999
DSC-4229/1
1 page  
IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
EXTENDEDCOMMERCIALTEMPERATURERANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Parameter
Output HIGH Voltage
Test Conditions(1)
VCC = 2.3V to 3.6V
IOH = – 0.1mA
Min.
VCC – 0.2
Max. Unit
—V
VCC = 2.3V
IOH = – 6mA
2—
VCC = 2.3V
IOH = – 12mA
1.7 —
VCC = 2.7V
2.2 —
VCC = 3.0V
2.4 —
VCC = 3.0V
IOH = – 24mA
2.2 —
VOL Output LOW Voltage
VCC = 2.3V to 3.6V
IOL = 0.1mA
— 0.2 V
www.DataSheet4U.com
VCC = 2.3V
IOL = 6mA
IOL = 12mA
— 0.4
— 0.7
VCC = 2.7V
IOL = 12mA
— 0.4
VCC = 3.0V
IOL = 24mA
— 0.55
NOTE:
LVC Link
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
CPD
CPD
Parameter
Power Dissipation Capacitance per bus exchanger Outputs enabled
Power Dissipation Capacitance per bus exchanger Outputs disabled
Test Conditions
CL = 0pF, f = 10Mhz
Typical
Unit
pF
pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.7V±0.2V
Symbol
Parameter
Min. Max.
tPLH Propagation Delay
tPHL AX to 1BX or Ax to 2BX
tPLH Propagation Delay
tPHL 1BX to AX or 2BX to AX
tPLH Propagation Delay
tPHL LEXB to AX
tPLH Propagation Delay
tPHL LEA1B to 1BX or LEA2B to 2BX
tPLH Propagation Delay
tPHL SEL to AX
tPZH Output Enable Time
tPZL OEA to AX, OE1B to 1BX, or OE2B to 2BX
tPHZ Output Disable Time
tPLZ OEA to AX, OE1B to 1BX, or OE2B to 2BX
1.5 5.7
1.5 6.1
1.5 6.1
1.5 6.1
1.5 6.3
1.5 6.7
1.5 5.9
tSU Set-Up Time, HIGH or LOW Data to Latch
1—
tH Hold Time, Latch to Data
1.2 —
tW Pulse Width, Latch HIGH
3—
tSK(o) Output Skew (2)
——
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
VCC = 3.3V±0.3V
Min. Max.
1.5 5
1.5 5.2
1.5 5.2
1.5 5
1.5 5.2
1.5 5.5
1.5 5.2
1—
1—
3—
— 500
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
5 Page | ||
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