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PDF IDT74LVC138A Data sheet ( Hoja de datos )
| Número de pieza | IDT74LVC138A | |
| Descripción | 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74LVC138A
3.3VCMOS3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
3.3V CMOS
3-LINE TO 8-LINE
DECODER/DEMULTIPLEXER
WITH 5 VOLT TOLERANT I/O
INDUSTRIALTEMPERATURERANGE
IDT74LVC138A
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
www.Data•ShReaeitl4-Uto.-cRomail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in QSOP, SOIC, SSOP, and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
The LVC138A 3-line to 8-line decoder/demultiplexer is built using
advanced dual metal CMOS technology. This device is designed for high-
performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high performance memory systems, this
decoder minimizes the effects of system decoding. When employed with
high-speed memories utilizing a fast enable circuit, the delay times of these
decoders and the enable time of the memory are usually less than the typical
access time of the memory. This means that the effective system delay
introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs
select one of eight output lines. Two active-low enable inputs and one active-
high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external invert-
ers and a 32-line decoder requires only one inverter. An enable input can
be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC138A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
FUNCTIONAL BLOCK DIAGRAM
Select
Inputs
1
A
2
B
3
C
Enable
Inputs
6
G1
4
G2A
5
G2B
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
7
Y7
Data
Outputs
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
©1999 Integrated Device Technology, Inc.
1
AUGUST 1999
DSC-4722/1
1 page  
IDT74LVC138A
3.3VCMOS3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
VCC(1)= 2.5V±0.2V
VLOAD
2 x Vcc
VIH Vcc
VT Vcc / 2
VLZ 150
VHZ 150
CL 30
VCC(2)= 3.3V±0.3V & 2.7V
6
2.7
1.5
300
300
50
Unit
V
V
V
mV
mV
pF
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
Propagation Delay
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
LVC QUAD Link
www.DataSheet4U.com
Pulse(1, 2)
Generator
VIN
VCC
VOUT
D.U.T.
500Ω
VLOAD
Open
GND
RT
500Ω
CL
Test Circuit for All Outputs
LVC QUAD Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
LVC QUAD Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
OUTPUT
NORMALLY
SWITCH
CLOSED
LOW
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
VLOAD/2
VT
tPHZ
VT
0V
VIH
VT
0V
VLOAD/2
VLZ
VOL
VOH
VHZ
0V
LVC QUAD Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA
INPUT
TIMING
INPUT
SYNCHRONOUS
CONTROL
ASYNCHRONOUS
CONTROL
tSU tH
tREM
tSU tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC QUAD Link
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
Pulse Width
VT
VT
LVC QUAD Link
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74LVC138A.PDF ] | |
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