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PDF HY27US561M Data sheet ( Hoja de datos )
| Número de pieza | HY27US561M | |
| Descripción | 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash | |
| Fabricantes | Hynix Semiconductor | |
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HY27SS(08/16)561M Series
HY27US(08/16)561M Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Document Title
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory
Revision History
No. History
0.0 Initial Draft
0.1 Renewal Product Group
www.DataShee0t.42U.cAopmpend 1.8V Operation Product to Data sheet
Insert Spare Enable function for GND Pin(#6)
- In case of Reading or Programming, GND Pin(#6) should be Low
or High.
0.3 - Change the test condition of Stand-by current-Refer to Table 13.
Change CSP Package name & thickness
- Name : VFBGA -> FBGA
- Thickness : 1.0mm(max) -> 1.2mm(max)
1) Delete Cache Program Mode
0.4
2) Modify the description of Device Operations
- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read
Disabled(Enabled) (Page23)
1) change FBGA dimension
0.5 : Thickness : 1.2mm(max) -> 1.0mm(max)
2) Edit Fig.33 read operation with CE don't care
1) Change TSOP1,WSOP1,FBGA package dimension
0.6 - Change TSOP1,WSOP1,FBGA mechanical data
- Inches parameter has been excluded from the mechanical data table
1) Change TSOP1, WSOP1, FBGA package dimension
0.7 2) Edit TSOP1, WSOP1 package figures
3) Change FBGA package figure
Draft Date
Jul. 10. 2003
Dec. 08. 2003
Dec. 08. 2003
Mar. 08. 2004
Jun. 01. 2004
Sep. 24. 2004
Oct. 18. 2004
Oct. 20. 2004
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.7 / Oct. 2004
1
1 page  
HY27SS(08/16)561M Series
HY27US(08/16)561M Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
NC 1
NC
48 NC
NC
NC
NC
1
48
NC NC NC
NC NC NC
NC
I/O7
NC
GND
I/O6
GND
RB
I/O5
RB
RE
I/O4
RE
CE NC CE
NC NC NC
NC NC NC
Vcc
Vss
NC
1123
NAND Flash
(x8)
3376
Vcc
Vss
NC
Vcc
Vss
NC
1123
NAND Flash
(x16)
3376
NC NC NC
CLE NC CLE
www.DataSheet4AWULEE.com
I/O3
I/O2
ALE
WE
WP
I/O1
WP
NC
I/O0
NC
NC NC NC
NC NC NC
NC NC NC
NC 24
25 NC
NC 24
25
Figure 3. 48-TSOP1 Contactions, x8 and x16 Device
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
NC
NC
Vcc
NC
NC
NC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
NC 1
NC
48
NC
NC
NC
GND
RB
RE
CE
NC
NC
Vcc
Vss
NC
NC
1123
NAND Flash
WSOP1
3376
(x8)
CLE
ALE
WE
WP
NC
NC
NC
NC
NC 24
25
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
Figure 4. 48-WSOP1 Contactions, x8 Device
Rev 0.7 / Oct. 2004
5
5 Page 
HY27SS(08/16)561M Series
HY27US(08/16)561M Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Table 2. Bus Operation
BUS Operation
Command Input
Address Input
Data Input
Data Output
Write Protect
Standby
CE ALE CLE RE WE WP
VIL
VIL
VIH
VIH
Rising
X(2)
VIL
VIH
VIL
VIH Rising
X
VIL
VIL
VIL
VIH Rising
X
VIL
VIL
VIL
Falling
VIH
X
X X X X X VIL
VIH X X X X X
www.DataShNeoetet4: U(1.)coOnmly for x16 devices.
(2) WP must be VIH when issing a program or erase command.
Table 3: Address Insertion, x8 Devices
Bus Cycle
1st Cycle
2nd Cycle
3rd Cycle
I/O7
A7
A16
A24
I/O6
A6
A15
A23
I/O5
A5
A14
A22
I/O4
A4
A13
A21
I/O3
A3
A12
A20
I/O0 - I/O7
Command
Address
Data Input
Data Output
X
X
I/O8 - I/O15(1)
X
X
Data Input
Data Output
X
X
I/O2
A2
A11
A19
I/O1
A1
A10
A18
I/O0
A0
A9
A17
Note: (1). A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
(2). Any additional input cycles will be ignored with tALS > 0ns.
Table4: Address Insertion, x16 Devices
Bus Cycle
1st Cycle
2nd Cycle
3rd Cycle
I/O8-IO15
L(1)
L(1)
L(1)
I/O7
A7
A16
A24
I/O6
A6
A15
A23
I/O5
A5
A14
A22
I/O4
A4
A13
A21
Note: (1). L must be set ''LOW''.
(2). A8 is Don't Care in x16 devices.
(3). Any additional input cycles will be ignored with tALS > 0ns.
(4). A1 is the Least Significant Address for x16 devices.
(5). The 01h Command is not used in x16 devices.
I/O3
A3
A12
A20
I/O2
A2
A11
A19
I/O1
A1
A10
A18
I/O0
A0
A9
A17
Rev 0.7 / Oct. 2004
11
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