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PDF HYI18TC256160AF Data sheet ( Hoja de datos )
| Número de pieza | HYI18TC256160AF | |
| Descripción | 256-Mbit Double-Data-Rate-Two SDRAM | |
| Fabricantes | Qimonda | |
| Logotipo |  |
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November 2007
HYB18TC256800AF
HYB18TC256160AF
HYI18TC256800AF
H Y I 1 8 T C 2 5 6 1 6 0 A Fwww.DataSheet4U.com
256-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.3
Date: 2007-11-23
1 page  
Internet Data Sheet
HY[B/I]18TC256[80/16]0AF
256-Mbit Double-Data-Rate-Two SDRAM
www.DataSheePt4roUd.cuocmt Type1)
Org. Speed
TABLE 2
Ordering Information for RoHS Compliant Products
CAS-RCD-RP Clock (MHz) Package
Latencies2)3)4)
Note5)
Standard Temperature Range (0 °C - +85 °C)
DDR2-800E( 6-6-6)
HYB18TC256800AF-2.5 ×8 DDR2-800E 6-6-6
400 PG-TFBGA-60
HYB18TC256160AF-2.5 ×16 DDR2-800E 6-6-6
400 PG-TFBGA-84
DDR2-800D( 5-5-5)
HYB18TC256160AF-25F ×16 DDR2-800D 5-5-5
400 PG-TFBGA-84
DDR2-667D( 5-5-5)
HYB18TC256800AF-3S ×8 DDR2-667D 5-5-5
333 PG-TFBGA-60
HYB18TC256160AF-3S ×16 DDR2-667D 5-5-5
333 PG-TFBGA-84
DDR2-533C( 4-4-4)
HYB18TC256800AF-3.7 ×8 DDR2-533C 4-4-4
266 PG-TFBGA-60
HYB18TC256160AF-3.7 ×16 DDR2-533C 4-4-4
266 PG-TFBGA-84
DDR2-400B( 3-3-3)
HYB18TC256800AF-5 ×8 DDR2-400B 3-3-3
200 PG-TFBGA-60
HYB18TC256160AF-5 ×16 DDR2-400B 3-3-3
200 PG-TFBGA-84
Industrial Temperature Range (–40 °C - +85 °C)
DDR2-800E( 6-6-6)
HYI18TC256160AF-2.5 ×16 DDR2-800E 6-6-6
400 PG-TFBGA-84
HYI18TC256800AF-2.5 ×8 DDR2-800E 6-6-6
400 PG-TFBGA-60
DDR2-800D( 5-5-5)
HYI18TC256160AF-25F ×16 DDR2-800D 5-5-5
400 PG-TFBGA-84
DDR2-667D( 5-5-5)
HYI18TC256800AF-3S ×8 DDR2-667D 5-5-5
333 PG-TFBGA-60
HYI18TC256160AF-3S ×16 DDR2-667D 5-5-5
333 PG-TFBGA-84
DDR2-533C( 4-4-4)
HYI18TC256160AF-3.7 ×16 DDR2-533C 4-4-4
266 PG-TFBGA-84
HYI18TC256800AF-3.7 ×8 DDR2-533C 4-4-4
266 PG-TFBGA-60
DDR2-400B( 3-3-3)
HYI18TC256800AF-5
×8 DDR2-400B 3-3-3
200 PG-TFBGA-60
HYI18TC256160AF-5
×16 DDR2-400B 3-3-3
200 PG-TFBGA-84
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Nomenclature" of this datasheet.
2) CAS: Column Address Strobe
3) RCD: Row Column Delay
4) RP: Row Precharge
Rev. 1.3, 2007-11
03062006-H3V1-XJT4
5
Date: 2007-11-23
5 Page 
Internet Data Sheet
HY[B/I]18TC256[80/16]0AF
256-Mbit Double-Data-Rate-Two SDRAM
2.2 Configuration for TFBGA-84
The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 7 and Table 8 respectively.
www.DataSheet4U.com
Ball#
Name
Ball
Type
Buffer
Type
Clock Signals ×16 Organization
J8 CK I
K8 CK I
K2
CKE
I
Control Signals ×16 Organization
K7
RAS
I
L7
CAS
I
K3 WE I
L8 CS I
Address Signals ×16 Organization
L2 BA0 I
L3 BA1 I
M8 A0 I
M3 A1 I
M7 A2 I
N2 A3 I
N8 A4 I
N3 A5 I
N7 A6 I
P2 A7 I
P8 A8 I
P3 A9 I
M2 A10 I
AP I
P7 A11 I
R2 A12 I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
TABLE 6
Configuration
Clock Signal CK, CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Chip Select
Bank Address Bus 1:0
Address Signal 12:0, Address Signal 10/Autoprecharge
Rev. 1.3, 2007-11
03062006-H3V1-XJT4
11
Date: 2007-11-23
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HYI18TC256160AF.PDF ] | |
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