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PDF HYI18T256400B Data sheet ( Hoja de datos )
| Número de pieza | HYI18T256400B | |
| Descripción | 256-Mbit Double-Data-Rate-Two SDRAM | |
| Fabricantes | Qimonda | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HYI18T256400B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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July 2007
HY[B/I]18T256400B[C/F](L)
HY[B/I]18T256800B[C/F](L)
HY[B/I]18T256160B[C/F](L)
www.DataSheet4U.com
256-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.11
1 page  
Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
1.2 Description
The 256-Mbit Double-Data-Rate-Two SDRAM is a high-
speed CMOS Synchronous DRAM device containing
268,435,456 bits and internally configured as a quad-bank
DRAM. The device is organized as either 16 Mbit × 4 I/O ×
4 banks, 8 Mbit × 8 I/O × 4 banks or 4 Mbit ×16 I/O × 4 banks
www.DataSheceht4ipU..coTmhese synchronous devices achieve high speed
transfer rates starting at 400 Mb/sec/pin for general
applications. See Table 1 for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
• Posted CAS with additive latency,
• Write latency = read latency - 1,
• Normal and weak strength data-output driver,
• Off-Chip Driver (OCD) impedance adjustment
• On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A is used to convey row, column and bank address
information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in P(G)-TFBGA-60 and P(G)-
TFBGA-84 packages.
Rev. 1.11, 2007-07
11172006-LBIU-F1TN
5
5 Page 
Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
L8
A13 I
SSTL
NC – –
Data Signals ×4×8 organization
C8
www.DataSheeCt42U.com
DQ0 I/O SSTL
DQ1 I/O SSTL
D7 DQ2 I/O SSTL
D3 DQ3 I/O SSTL
D1 DQ4 I/O SSTL
D9 DQ5 I/O SSTL
B1 DQ6 I/O SSTL
B9 DQ7 I/O SSTL
Data Strobe×4×8 organizations
B7 DQS I/O SSTL
A8 DQS I/O SSTL
Data Strobe ×8 organisation
B3
RDQS O
SSTL
A2
RDQS O
SSTL
Data Mask ×4×8 organizations
B3
DM I
SSTL
Power Supplies ×4×8 organization
A9,C1,C3,C7,C VDDQ
9
PWR –
A1
A7,B2,B8,D2,D
8
VDD
VSSQ
PWR
PWR
–
–
A3,E3
VSS PWR –
Power Supplies ×4×8 organizations
E2
VREF
AI
E1
VDDL
PWR
E9,H9,L1 VDD PWR
E7
VSSDL
PWR
J1,K9
VSS PWR
Not Connected ×4×8 organization
–
–
–
–
–
G1, L3,L7, L8 NC
NC –
Not Connected ×4 organization
A2, B1, B9, D1, NC
D9
NC –
Other Balls ×4×8 organizations
F9
ODT
I
SSTL
Function
Address Signal 13
Note: 256 Mbit components and
Data Signal 3:0
Data Signal 7:4
Data Strobe
Read Data Strobe
Data Mask
I/O Driver Power Supply
Power Supply
I/O Driver Power Supply
Power Supply
I/O Reference Voltage
Power Supply
Power Supply
Power Supply
Power Supply
Not Connected
Not Connected
On-Die Termination Control
Rev. 1.11, 2007-07
11172006-LBIU-F1TN
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HYI18T256400B.PDF ] | |
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