T6B70BF Datasheet PDF - Toshiba Semiconductor
| Part Number | T6B70BF | |
| Description | Interface IC | |
| Manufacturers | Toshiba Semiconductor | |
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There is a preview and T6B70BF download ( pdf file ) link at the bottom of this page. Total 15 Pages | ||
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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6B70BF
Interface IC for Water Heater
T6B70BF
The T6B70BF incorporates two-channel 4-bit DA converter, a
pseudo sine wave generator and an external analog signal
detection/non-detection circuit. It is designed to be used mainly
for communication between water heater and control unit.
www.DataSheet4U.com
Features
· On-chip two-channel 4-bit DA converter (opposite polarities)
· On-chip pseudo sine wave generator (external clock/16)
· On-chip external analog signal detection/non-detection circuit
· On-chip two-channel analog switch
Block Diagram
Weight: 0.16 g (typ.)
OSCIN 1
OSCOUT 2
FOUT 3
SCTL 4
SW1IN 14
SW1OUT 15
SW2IN 11
SW2OUT 10
RESET 5
Divide-by-
16 unit
Modulation
control circuit
Reset
circuit
Pseudo
sine wave
0°C
generator 180°C
Waveform
initialization block
4-bit
DA converter
4-bit
DA converter
13 SOUT+
12 SOUT−
16 VDD
Zero-cross
waveform
shaping circuit
Amplifier input
circuit
Cycle measurement counter
Analog signal
detection/non-detection
Output buffer
7 AMPIN
6 AMPOUT
8 VSS
9 DOUT
1 2003-03-13
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T6B70BF
(3) Function description and timing chart of the sending block
When modulation control input ( SCTL ) is in High-level, pseudo sine wave output is held at 0° of
the phase angle of pseudo sine wave. When modulation control input changes from High-level to
Low-level, the pseudo sine wave output (SOUT+) starts from −90° (SOUT− starts from +90°).
In this case, the time which takes to turn ON is as follows.
td (ON) < 500 ns
When modulation control input changes from Low-level to High-level, the phase angle is forcibly
held at 0°, regardless of the phase of the pseudo sine wave output. (the pseudo sine wave output is
stopped). In this case, the time which takes to turn OFF is as follows.
td (OFF) < 1 µs
SCTL
www.DataSheet4SUO.cUoTm+
pseudo
sine
wave
td (ON)
output
(SOUT− output pin has the
opposite polarity)
td (OFF)
(4) Function description and timing chart of the receiving block
When it is ready to receive amplifier input signal, the time T (DET) which takes to change from
High to Low at DOUT pin is within the time which 9 to 15 waves to pass. In this case, one wave is
referenced to 16 Fosc clocks. The time width is determined by the internal clock and amplifier input
signal. The timings of the internal clock and internal detection signal in the majority logic circuit are
synchronous with each other. When input signals with the cycle, which is within the range specified
by the frequency window, are detected (or not detected) sequentially, this rule is valid (the majority
rule).
Amplifier input
T (DET)
T (DET)
DOUT
Note 1: Any communication protocol is used, however, it takes 15 carrier waves to pass when the signal changes its
state.
5 2003-03-13
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for T6B70BF electronic component. |
| Information | Total 15 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ T6B70BF.PDF Datasheet ] | |
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