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PDF T6B70AF Data sheet ( Hoja de datos )
| Número de pieza | T6B70AF | |
| Descripción | Interface IC | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de T6B70AF (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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Preliminary TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6B70AF
Interface IC for Water Heater
T6B70AF
The T6B70A incorporates two-channel 4-bit DA converter, a
pseudo sine wave generator and an external analog signal
detection/non-detection circuit. It is designed to be used mainly
for communication between water heater and control unit.
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Features
· On-chip two-channel 4-bit DA converter (opposite polarities)
· On-chip pseudo sine wave generator (external clock/16)
· On-chip external analog signal detection/non-detection circuit
· On-chip two-channel analog switch
Block Diagram
Weight: 0.16 g (typ.)
OSCIN 1
OSCOUT 2
FOUT 3
SCTL 4
SW1IN 14
SW1OUT 15
SW2IN 11
SW2OUT 10
RESET 5
Divide-by-
16 unit
Modulation
control circuit
Reset
circuit
Pseudo
sine wave
0°C
generator 180°C
Waveform
initialization block
4-bit
DA converter
4-bit
DA converter
13 SOUT+
12 SOUT−
16 VDD
Zero-cross
waveform
shaping circuit
Amplifier input
circuit
Cycle measurement counter
Analog signal
detection/non-detection
Output buffer
7 AMPIN
6 AMPOUT
8 VSS
9 DOUT
1 2002-02-28
1 page  
T6B70AF
(3) Function description and timing chart of the sending block
When modulation control input ( SCTL ) is in High-level, pseudo sine wave output is held at 0° of
the phase angle of pseudo sine wave. When modulation control input changes from High-level to
Low-level, the pseudo sine wave output (SOUT+) starts from −90° (SOUT− starts from +90°).
In this case, the time which takes to turn ON is as follows.
td (ON) < 500 ns
When modulation control input changes from Low-level to High-level, the phase angle is forcibly
held at 0°, regardless of the phase of the pseudo sine wave output. (the pseudo sine wave output is
stopped). In this case, the time which takes to turn OFF is as follows.
td (OFF) < 1 µs
SCTL
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pseudo
sine
wave
td (ON)
output
(SOUT− output pin has the
opposite polarity)
td (OFF)
(4) Function description and timing chart of the receiving block
When it is ready to receive amplifier input signal, the time T (DET) which takes to change from
High to Low at DOUT pin is within the time which 9 to 15 waves to pass. In this case, one wave is
referenced to 16 Fosc clocks. The time width is determined by the internal clock and amplifier input
signal. The timings of the internal clock and internal detection signal in the majority logic circuit are
synchronous with each other. When input signals with the cycle, which is within the range specified
by the frequency window, are detected (or not detected) sequentially, this rule is valid (the majority
rule).
Amplifier input
T (DET)
T (DET)
DOUT
Note 1: Any communication protocol is used, however, it takes 15 carrier waves to pass when the signal changes its
state.
Note 2: When DOUT output is held at Low, low frequency wave as calculated below is detected.
(min)
(typ.)
(max)
f
18 × n + 17
~
f
18 × n + 16
~
f
18 × n + 15
n = Integer from 0 to 12
f: Source clock
When two carrier waves or more are used according to a system, contact Toshiba.
5 2002-02-28
5 Page 
(13) Low-level output voltage
4 MHz
PG
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1 OSCIN
VDD 16
5V
2 OSCOUT SW1OUT 15
3 FOUT
SW1IN 14
4 SCTL
SOUT+ 13
5 RESET
SOUT− 12
6 AMPOUT SW2IN 11
7 AMPIN SW2OUT 10
8 VSS
DOUT 9
VOLDOUT V
(14) Input dynamic range
T6B70AF
4 MHz
PG
Monitor
VAMPIN
1 OSCIN
VDD 16
2 OSCOUT SW1OUT 15
3 FOUT
SW1IN 14
4 SCTL
SOUT+ 13
5 RESET
SOUT− 12
6 AMPOUT SW2IN 11
7 AMPIN SW2OUT 10
8 VSS
DOUT 9
5V
(15) Pull-up resistance 1
Pull-up resistance 2
1 OSCIN
VDD 16
2 OSCOUT SW1OUT 15
3 FOUT
SW1IN 14
4 SCTL
SOUT+ 13
IILRAPU1 5 RESET
IILRAPU2 6 AMPOUT
SOUT− 12
SW2IN 11
A 7 AMPIN SW2OUT 10
8 VSS
DOUT 9
5V
(17) Amplifier input bias voltage
VBIAS V
1 OSCIN
VDD 16
2 OSCOUT SW1OUT 15
3 FOUT
SW1IN 14
4 SCTL
SOUT+ 13
5 RESET
SOUT− 12
6 AMPOUT SW2IN 11
7 AMPIN SW2OUT 10
8 VSS
DOUT 9
5V
(16) Pull-down resistor 1
Pull-down resistor 2
1 OSCIN
VDD 16
2 OSCOUT SW1OUT 15
3 FOUT
SW1IN 14
4 SCTL
SOUT+ 13
IIHRAPD1 5 RESET
IIHRAPD2 6 AMPOUT
SOUT− 12
SW2IN 11
A 7 AMPIN SW2OUT 10
VIN
8 VSS
DOUT 9
5V
(18) Amplifier input sensitivity
4 MHz
PG
Monitor
250 kHz Vp-p
sine wave
1 OSCIN
VDD 16
2 OSCOUT SW1OUT 15
3 FOUT
SW1IN 14
4 SCTL
SOUT+ 13
5 RESET
SOUT− 12
6 AMPOUT SW2IN 11
7 AMPIN SW2OUT 10
8 VSS
DOUT 9
5V
11 2002-02-28
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet T6B70AF.PDF ] | |
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