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PDF HY5R256HC745 Data sheet ( Hoja de datos )
| Número de pieza | HY5R256HC745 | |
| Descripción | RDRAM | |
| Fabricantes | Hynix Semiconductor | |
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Direct RDRAM™
256/288-Mbit (512Kx16/18x32s) Preliminary
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 256/288-Mbit Direct Rambus DRAMs (RDRAM)are
extremely high-speed CMOS DRAMs organized as 16M
words by 16 or 18 bits. The use of Rambus Signaling Level
www.DataSh(eReSt4LU).ctoemchnology permits 600MHz to 800MHz transfer
rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of
sustained data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Features
0 Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
0 Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
0 Advanced power management:
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
0 Organization: 2Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
0 Uses Rambus Signaling Level (RSL) for up to 800MHz
operation
Figure 1: Direct RDRAM uBGA Package
The 256/288-Mbit Direct RDRAMs are offered in a uBGA
package suitable for desktop as well as low-profile add-in
card and mobile applications.
Direct RDRAMs operate from a 2.5 volt supply.
Key Timing Parameters / Part Numbers
Organizationa
I/O Freq. Core Access Time
MHz
(ns)
512Kx16x32s
600
53
512Kx16x32s
512Kx16x32s
711
800
45
45
512Kx16x32s
512Kx18x32s
512Kx18x32s
512Kx18x32s
512Kx18x32s
800
600
711
800
800
40
53
45
45
40
Part
Number
HY5R256HC653
HY5R256HC745
HY5R256HC845
HY5R256HC840
HY5R288HC653
HY5R288HC745
HY5R288HC845
HY5R288HC840
a. The bank “32s” designation indicates that this RDRAM core is
composed of 32 banks which use a “split” bank architecture.
Rev. 0.9 / Dec.2000
1
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of
circuits described. No patent licenses are implied.
1 page  
Direct RDRAM™
256/288-Mbit (512Kx16/18x32s) Preliminary
General Description
Figure 2: is a block diagram of the 256/288 Mbit Direct
RDRAM. It consists of two major blocks: a “core” block
built from banks and sense amps similar to those found in
other types of DRAM, and a Direct Rambus interface block
which permits an external controller to access this core at up
to 1.6GB/s.
Control Registers: The CMD, SCK, SIO0, and SIO1
www.DataShpeients4Uap.cpoemar in the upper center of Figure 2:. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The REFR value is used for tracking the last refreshed row.
Most importantly, the five bit DEVID specifies the device
address of the RDRAM on the Channel.
Clocking: The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
DQA,DQB Pins: These 18 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multi-
plexed from/to two 72-bit data paths (running at one-eighth
the data frequency) inside the RDRAM.
Banks: The 32Mbyte core of the RDRAM is divided into
32 x 1Mbyte banks, each organized as 512 rows, with each
row containing 128 dualocts(2K bytes), and each dualoct
containing 16 bytes. A dualoct is the smallest unit of data
that can be addressed.
Sense Amps: The RDRAM contains 34 sense amps.
Each sense amp consists of 1K bytes of fast storage (512
bytes for DQA and 512 bytes for DQB) and can hold one-
half of one row of one bank of the RDRAM. The sense amp
may hold any of the 1024 half-rows of an associated bank.
However, each sense amp is shared between two adjacent
banks of the RDRAM (except for sense amps 0, 15, 16, and
31). This introduces the restriction that adjacent banks may
not be simultaneously accessed.
RQ Pins: These pins carry control and address informa-
tion. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
ROW Pins: The principle use of these three pins is to
manage the transfer of data between the banks and the sense
amps of the RDRAM. These pins are de-multiplexed into a
24-bit ROWA (row-activate) or ROWR (row-operation)
packet.
COL Pins: The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM. These pins are de-multi-
plexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
ACT Command: An ACT (activate) command from an
ROWA packet causes one of the 512 rows of the selected
bank to be loaded to its associated sense amps (two 512
bytes sense amps for DQA and two for DQB).
PRER Command: A PRER (precharge) command from
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be acti-
vated.
RD Command: The RD (read) command causes one of
the 64 dualocts of one of the sense amps to be transmitted on
the DQA/DQB pins of the Channel.
WR Command: The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 128 dualocts of one of the sense amps during a subse-
quent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turn-
around.
PREC Precharge: The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except that a
precharge operation is performed at the end of the column
operation. These commands provide a second mechanism
for performing precharge.
PREX Precharge: After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
Rev. 0.9 / Dec.2000
5
5 Page 
Direct RDRAM™
256/288-Mbit (512Kx16/18x32s) Preliminary
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
ROW2
..ROW0
ACT a0
COL4
..COL0
www.DataSheet4U.com
DQA8..0
DQB8..0
Transaction a: WR
WR a1
tRTR
retire (a1)
MSK (a1)
tCWD
D (a1)
PRER a2
ACT b0
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba}
CTM/CFM
COLM Packet
T17 T18 T19
T20 T19
CTM/CFM
D Packet
T20 T21
T22
COL4
COL3
COL2
COL1
COL0
MA7 MA5 MA3 MA1
M=1 MA6 MA4 MA2 MA0
MB7 MB4 MB1
MB6 MB3 MB0
MB5 MB2
DQB8
DB8 DB17 DB26 DB35 DB45 DB53 DB62 DB71
DQB7
DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70
DQB1
DB1 DB10 DB19 DB28 DB37 DB46 DB55 DB64
DQB0
DB0 DB9 DB18 DB27 DB36 DB45 DB54 DB63
When M=1, the MA and MB
fields control writing of
individual data bytes.
When M=0, all data bytes are
written unconditionally.
Each bit of the MB7..MB0 field
controls writing (=1) or no writing
(=0) of the indicated DB bits when
the M bit of the COLM packet is one.
DQA8
MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7
DA8 DA17 DA26 DA35 DA45 DA53 DA62 DA71
DQA7 DA7 DA16 DA25 DA34 DA44 DA52 DA61 DA70
DQA1 DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64
Each bit of the MA7..MA0 field
controls writing (=1) or no writing
(=0) of the indicated DA bits when
the M bit of the COLM packet is one.
DQA0
DA0 DA9 DA18 DA27 DA36 DA45 DA54 DA63
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7
Figure 5: Mapping Between COLM Packet and D Packet for WR Command
Rev.0.9 / Dec.2000
11
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