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PDF LM2743 Data sheet ( Hoja de datos )
| Número de pieza | LM2743 | |
| Descripción | N-Channel FET Synchronous Buck Regulator Controller for Conversion from 3.3V | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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April 2004
LM2743
N-Channel FET Synchronous Buck Regulator Controller
for Conversion from 3.3V
General Description
The LM2743 is a high-speed, N-Channel synchronous buck
regulator controller with a 2%, 0.6V feedback reference volt-
age intended to make down conversion from 3.3V to as low
as 0.6V easy. A fixed-frequency voltage-mode PWM control
architecture is used, that is adjustable from 50kHz to 2MHz
through an external resistor. This wide range of PWM fre-
quencies gives the power supply designer the flexibility to
make tradeoffs among component size, cost, noise and
efficiency. The power MOSFETs can run on a separate 1V to
16V (Input Voltage, VIN) (Note 2) rail while the regulator is
biased from a 3V to 6V (IC Input Voltage, VCC), 2mA rail. A
power-good flag, precision shutdown threshold and soft start
features make power supply tracking and sequencing easy.
The LM2743 employs output under-voltage and over-voltage
flag, and current limit. Current limit is achieved by monitoring
the voltage drop across the on resistance of the low-side
MOSFET. The adaptive non-overlapping MOSFET gate driv-
ers help avoid potential shoot-through problems while main-
taining high efficiency. Both high-side and low-side MOS-
FETs are the lower cost N-Channel type, and the IC can
accept a bootstrap structure to saturate the high-side MOS-
FET for highest efficiency.
Features
n MOSFET input voltage (VIN) from 1V to 16V (Note 2)
n IC input voltage (VCC) from 3V to 6V
n Output voltage adjustable down to 0.6V
n Power good flag and output enable
n Output over-voltage and under-voltage flag
n FB voltage: 2% over temperature
n Current limit without series sense resistor
n Adjustable soft start
n Tracking and sequencing with shutdown and soft start
pins
n Switching frequency from 50 kHz to 2 MHz
n TSSOP-14 package
Applications
n 3.3V Buck Regulation
n Set-Top Boxes/ Home Gateways
n Core Logic Regulators
n High-Efficiency Buck Regulation
Typical Application
© 2004 National Semiconductor Corporation DS200952
20095201
www.national.com
1 page  
Typical Performance Characteristics
Efficiency (VOUT = 1.2V)
VCC = 3.3V, FSW = 300kHz
Efficiency (VOUT = 2.5V)
VCC = 3.3V, FSW = 300kHz
Efficiency (VOUT = 3.3V)
VCC = 5V, FSW = 300kHz
20095240
20095257
VCC Operating Current vs Temperature
20095241
VCC Operating Current plus BOOT Current vs Frequency
FDS689A FET (TA = 25˚C)
20095261
BOOT Pin Current vs Temperature for
BOOT Voltage = 3.3V
FSW = 300kHz, FDS689A FET, No-Load
20095245
5
20095242
www.national.com
5 Page 
Application Information (Continued)
VFB = VOUT2 *(RFB2/(RFB1+RFB2))
Since VSS = VFB=0.6V, then
Tracking Equation
The total value of the track resistor divider (Figure 3), R3 and
R4, should be set below 10kΩ for better precision. Let
R4=1K, for VOUT1= 5V and VOUT2=1.8V, R3=136Ω.
20095208
FIGURE 4. Timing Behavior of Case 1
Case 2: Rise together until VOUT2=1.8V
20095210
FIGURE 6. Timing Behavior of Case 2
Case 3: VOUT2 starts rising 3.0ms after VOUT1
Assuming VOUT1 slew rate SRVSD = 1V/ms and voltage
divider ratio 1:3 (R3 = 500Ω and R4 = 1kΩ), the VSD slew rate
equals SRVSD = 0.333V/ms. During the delay time VSD
raises to 1.0V (VSD-IH) as shown in Figure 8. The delay time
is calculated from :
tDELAY = VSD-IH /SRVSD
tDELAY= 1.0(V) / 0.333(V/ms) = 3.0ms
20095209
FIGURE 5. Block Diagram of Case 2
VSS = VFB= 0.6V,
VOUT1 = VOUT2 = 1.8V
For R4=1kΩ, R3=500Ω (from Tracking Equation).
The soft start reaches 0.6V at VOUT1 equal 1.8V.
For VOUT1>1.8V, VOUT2 stays in regulation at 1.8V.
11
20095214
FIGURE 7. Block Diagram of Case 3
www.national.com
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet LM2743.PDF ] | |
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