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PDF 5070M0Y1V0 Data sheet ( Hoja de datos )
| Número de pieza | 5070M0Y1V0 | |
| Descripción | PF38F5070M0Y1V0 | |
| Fabricantes | Numonyx | |
| Logotipo |  |
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Numonyx™ StrataFlash® Cellular Memory
(M18)www.DataSheet4U.com
Product Features
Datasheet
High-Performance Read, Program and Erase
— 96 ns initial read access
— 108 MHz with zero wait-state synchronous
burst reads: 7 ns clock-to-data output
— 133 MHz with zero wait-state synchronous
burst reads: 5.5 ns clock-to-data output
— 8-, 16-, and continuous-word
synchronous-burst Reads
— Programmable WAIT configuration
— Customer-configurable output driver
impedance
— Buffered Programming:
2.0 µs/Word (typ), 512-Mbit 65 nm;
Block Erase: 0.9 s per block (typ)
— 20 µs (typ) program/erase suspend
Architecture
— 16-bit wide data bus
— Multi-Level Cell Technology
— Symmetrically-Blocked Array Architecture
— 256-Kbyte Erase Blocks
— 1-Gbit device: Eight 128-Mbit partitions
— 512-Mbit device: Eight 64-Mbit partitions
— 256-Mbit device: Eight 32-Mbit partitions.
— 128-Mbit device: Eight 16-Mbit partitions.
— Read-While-Program and Read-While-Erase
— Status Register for partition/device status
— Blank Check feature
Quality and Reliability
— Expanded temperature: –30 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ X Process Technology (65 nm)
— ETOX™ IX Process Technology (90 nm)
Power
— Core voltage: 1.7 V - 2.0 V
— I/O voltage: 1.7 V - 2.0 V
— Standby current: 60 µA (typ) for 512-Mbit,
65 nm
— Deep Power-Down mode: 2 µA (typ)
— Automatic Power Savings mode
— 16-word synchronous-burst read current:
23 mA (typ) @ 108 MHz; 24 mA (typ) @
133 MHz
Software
— Numonyx™ Flash Data Integrator
(Numonyx™ FDI) optimized
— Basic Command Set and Extended
Command Set compatible
— Common Flash Interface
Security
— OTP Registers:
64 unique pre-programmed bits
2112 user-programmable bits
— Absolute write protection with VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
Density and Packaging
— Density: 128-, 256-, and 512-Mbit, and 1-
Gbit
— Address-data multiplexed and non-
multiplexed interfaces
— x16D (105-ball) Flash SCSP
— x16C (107-ball) Flash SCSP
— 0.8 mm pitch lead-free solder-ball
Order Number: 309823-11
April 2008
1 page  
Numonyx™ StrataFlash® Cellular Memory (M18)
12.3 CFI Query Identification String .......................................................................... 111
12.4 Device Geometry Definition .............................................................................. 113
12.5 Numonyx-Specific Extended Query Table ............................................................ 114
13.0 Next State ............................................................................................................. 120
A AADM Mode ........................................................................................................... 128
B Additional Information .......................................................................................... 136
C Ordering Information ............................................................................................ 136
www.DataSheet4U.com
April 2008
Order Number: 309823-11
Datasheet
5
5 Page 
Numonyx™ StrataFlash® Cellular Memory (M18)
• Deep Power-Down (DPD) mode: DPD provides the lowest power consumption and
is enabled by programming in the Enhanced Configuration Register. DPD is initiatied
by asserting the DPD pin.
2.2
www.DataSheet4U.com
Configuration and Memory Map
The Numonyx™ StrataFlash® Cellular Memory device features a symmetrical block
architecture. The flash device main array is divided as follows:
• The main array of the 128-Mbit device is divided into eight 16-Mbit partitions. Each
parition is divided into eight 256-KByte blocks: 8 x 8 = 64 blocks in the main array
of a 128-Mbit device.
• The main array of the 256-Mbit device is divided into eight 32-Mbit partitions. Each
parition is divided into sixteen 256-KByte blocks: 8 x 16 = 128 blocks in the main
array of a 256-Mbit device.
• The main array of the 512-Mbit device is divided into eight 64-Mbit partitions. Each
parition is divided into thirty-two 256-KByte blocks: 8 x 32 = 256 blocks in the
main array of a 256-Mbit device.
• The main array of the 1-Gbit device is divided into eight 128-Mbit partitions. Each
parition is divided into sixty-four 256-KByte blocks: 8 x 64 = 512 blocks in the
main array of a 1-Gbit device.
Each block is divided into as many as two-hundred-fifty-six 1-KByte programming
regions. Each region is divided into as many as thirty-two 32-Byte segments.
Table 5: Main Array Memory Map (Sheet 1 of 2)
Partition
7
6
5
4
Mbit
128-Mbit Device
Blk Address
# Range
Mbit
256-Mbit Device
Blk Address
# Range
Mbit
63
07E0000-
07FFFFF
127
0FE0000-
0FFFFFF
16 32
64
56
0700000-
071FFFF
112
0E00000-
0E1FFFF
55
06E0000-
06FFFFF
111
0DE0000-
0DFFFFF
16 32
64
48
0600000-
061FFFF
96
0C00000-
0C1FFFF
47
05E0000-
05FFFFF
95
0BE0000-
0BFFFFF
16 32
64
40
0500000-
051FFFF
80
0A00000-
0A1FFFF
39
04E0000-
04FFFFF
79
09E0000-
09FFFFF
16 32
64
32
0400000-
041FFFF
64
0800000-
081FFFF
512-Mbit Device
Blk Address
# Range
Mbit
255
1FE0000-
1FFFFFF
128
224
1C00000-
1C1FFFF
223
1BE0000-
1BFFFFF
128
192
1800000-
181FFFF
191
17E0000-
17FFFFF
128
160
1400000-
141FFFF
159
13E0000-
13FFFFF
128
128
1000000-
101FFFF
1-Gbit Device
Blk Address
# Range
511
3FE0000-
3FFFFFF
448
3800000-
381FFFF
447
37E0000-
37FFFFF
384
3000000-
301FFFF
383
2FE0000-
2FFFFFF
320
2800000-
281FFFF
319
27E0000-
27FFFFF
256
2000000-
201FFFF
April 2008
309823-10
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 5070M0Y1V0.PDF ] | |
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