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PDF HY27SS08561A Data sheet ( Hoja de datos )
| Número de pieza | HY27SS08561A | |
| Descripción | (HY27xxxx561A) 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Document Title
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory
Revision History
Revision
www.DataSheet4U.comNo.
0.0
Initial Draft.
History
1) Change AC Parameter
tCRY(1.8V)
Before
50+tr(R/B#)
0.1
After
60+tr(R/B#)
2) Change 256Mb Package Type.
- WSOP package is changed to USOP package.
- Figure & dimension are changed.
1) Correct the test Conditions (DC Characteristics table)
Test Conditions (ICC1) Test Conditions (ILI, ILO)
Before
tRC=50ns,
CE#=VIL,
IOUT=0mA
VIN=VOUT=0 to 3.6V
After
tRC(1.8V=60ns,
3.3V=50ns)
CE#=VIL,
IOUT=0mA
VIN=VOUT=0 to Vcc (max)
2) Change AC Conditions table
0.2 3) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
4) Edit Copy Back Program operation step
5) Edit System Interface Using CE don’t care Figures.
6) Correct Address Cycle Map.
7) Change NOP (table 11)
Main Array Spare Array
Before
1
2
After
2
3
Draft Date Remark
Apr. 04. 2005 Preliminary
Jul. 07. 2005 Preliminary
Aug. 08. 2005 Preliminary
Rev 0.5 / Jun. 2006
1
1 page  
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HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
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Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
PRE
Data Input / Outputs (x16 Only)
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Power-On Read Enable, Lock Unlock
Table 1: Signal Names
Rev 0.5 / Jun. 2006
5
5 Page 
HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
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2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin
must be high. See figure 7 and table 12 for details of the timings requirements. Command codes are always applied on
IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. Three bus cycles are required to input the
addresses for the 256Mbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Com-
mand Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for commands
that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 8 and table 12 for details of
the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure
9 and table 12 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 10 to 14 and table 12 for details
of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.5 / Jun. 2006
11
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