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PDF LM2637 Data sheet ( Hoja de datos )
| Número de pieza | LM2637 | |
| Descripción | Motherboard Power Supply Solution with a 5-Bit Programmable Switching Controller and Two Linear Regulator Controllers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 1998
LM2637
Motherboard Power Supply Solution with a 5-Bit
Programmable Switching Controller and Two Linear
Regulator Controllers
General Description
The LM2637 provides a comprehensive embedded power
supply solution for motherboards hosting high performance
MPUs such as M II™, Pentium™ II, K6-2 and other similar
high performance MPUs. The LM2637 incorporates a 5-bit
programmable, synchronous buck switching controller and
two high-speed linear regulator controllers in a 24-pin SO
package.
Switching Section — The switching regulator controller fea-
tures a 5-bit programmable DAC, over-current and
over-voltage protection, under-voltage latch-off, a power
good signal, and output enable. The 5-bit DAC has a typical
tolerance of 1%. There are two user-selectable over-current
protection methods. One provides accurate over-current pro-
tection with the use of an external sense resistor. The other
saves cost by taking advantage of the rDS_ON of the
high-side FET. The over voltage protection provides two lev-
els of protection. The first level keeps the high-side FET off
and the low-side FET on. The second provides a gate signal
that can be used to fire an external SCR.
Linear Section — The two linear regulator controllers fea-
ture wide control bandwidth, N-FET and NPN transistor driv-
ing capability, and an adjustable output voltage. The wide
control bandwidth makes meeting fast load transient re-
sponse requirement such as that of the GTL+ bus an easy
job. In minimum configuration, the two controllers default to
1.5V and 2.5V respectively.
Both linear controllers have under voltage latch-off.
Features
n Provides 3 regulated voltages
n Power Good flag and output enable
n Under-voltage latch-off
Switching Section
n Synchronous rectification
n 5-bit DAC programmable from 3.5V to 1.3V
n Typical 1% DAC tolerance
n Switching frequency: 50 kHz to 1 MHz
n Two levels of over-voltage protection
n Two methods of over-current protection
n Adaptive non-overlapping FET gate drives
n Soft start without external capacitor
Linear Section
n N-FET and NPN driving capability
n Ultra fast response speed
n Output voltages default to 1.5V and 2.5V yet adjustable
Applications
n Embedded power supplies for PC motherboards
n Triple DC/DC power supplies
n Programmable high current DC/DC power supply
Pin Configuration
24-Lead SOIC
DS100848-1
Top View
NS Package Number M24B
M II™ is a trademark of Cyrix Corporation a wholly owned subsidiary of National Semiconductor Corporation.
Pentium™ is a trademark of Intel Corporation.
K6 is trademark of Advanced Micro Devices, Inc.
© 1999 National Semiconductor Corporation DS100848
www.national.com
1 page  
Block Diagram
Test Circuit
DS100848-30
FIGURE 1. LDO Controller Test Circuit
DS100848-2
5
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5 Page 
Applications Information (Continued)
buck regulator that needs to meet stringent load transient re-
quirement such as that of processor core voltage supply, a
2-pole-1-zero compensation network should suffice, such as
the one shown in Figure 6 (C1, C2, R1 and R2). This is be-
cause the ESR zero of the typical output capacitors is low
enough to make the control-to-output transfer function a
single-pole roll-off.
As an example, let us figure out the values of the compensa-
tion network components in Figure 6. Assume the following
parameters: R = 20Ω, RL = 20 mΩ, RC = 9 mΩ, L = 2 µH, C
= 7.5 mF, VIN = 5V, Vm = 2V and PWM frequency = 300 kHz.
Notice RL is the sum of the inductor DC resistance and the
on resistance of the FET’s.
The control-to-output transfer function is:
The ESR zero frequency is:
(5)
DS100848-9
FIGURE 5. Current Limit via Current Sense Resistor
For a given current limit value, the minimum RSENSE is deter-
mined by:
(4)
where VOCP is the over-current trip voltage and is typically
55 mV, see the Electrical Characteristic table. For example,
for a 20A current limit, the minimum RSENSE is 2.75 mΩ. If a
3 mΩ sense resistor is used instead, use appropriate values
of R1 and R2 to make the voltage across R1 to be VOCP when
the voltage across RSENSE is 60 mV.
The discrete current sense resistor usually has a very good
temperature coefficient and tolerance. A temperature coeffi-
cient of ±30 ppm/˚C is typical. Tolerance is usually ±1% or
±5%. Vishay Dale and IRC offer a broad range of discrete
sense resistors.
A PCB etch resistor can also be used as the RSENSE. The
advantage of that approach is flexible resistance, which will
result in minimum power loss. R1 and R2 may also be elimi-
nated. The drawback is too high a temperature coefficient,
typically +4000 ppm/˚C, which will result in a much less ac-
curate current limit than a discrete sense resistor. The cop-
per thickness of a PCB is usually of 5% tolerance.
Linear Section — There is no current limit function in the lin-
ear controllers. However, if there is ever a severe over-load,
the output voltage may drop below 0.63V, in which case the
under-voltage latch-off will provide the protection.
DESIGN CONSIDERATIONS
Control Loop Compensation
Switching Section — A switching regulator should be prop-
erly compensated to achieve a stable operation, tight regula-
tion and good dynamic performance. For a synchronous
The double pole frequency is:
(6)
(7)
The corresponding Bode plots are shown in Figure 7.
Notice since the ESR zero frequency is so low that the phase
doesn’t even go beyond −90˚. This makes the compensation
easier to do.
Since the DC gain and cutoff frequency (0 dB frequency) are
too low, some compensation is needed. Otherwise the low
DC gain will cause a poor line regulation, and the low cutoff
frequency may hurt transient response performance.
The transfer function for the 2-pole-1-zero compensation
network shown in Figure 6 is:
where
(8)
(9)
One of the poles is located at origin to help achieve the high-
est DC gain. So there are three parameters to determine, the
position of the zero, the position of the second pole, and the
constant A. To determine the cutoff frequency and phase
margin, the loop bode plots need to be generated. The loop
transfer function is:
TF = −TF1 x TF2
(10)
By choosing the zero close to the double pole position and
the second pole to half of the switching frequency, the closed
loop transfer function turns out to be very good.
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| PDF Descargar | [ Datasheet LM2637.PDF ] | |
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