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PDF 12F615 Data sheet ( Hoja de datos )
| Número de pieza | 12F615 | |
| Descripción | PIC12F615 | |
| Fabricantes | Microchip Technology | |
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www.DataSheet4U.com
PIC12F609/HV609
PIC12F615/HV615
Data Sheet
8-Pin Flash-Based, 8-Bit
CMOS Microcontrollers
* 8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
© 2006 Microchip Technology Inc.
Preliminary
DS41302A
1 page  
PIC12F609/615/12HV609/615
8-Pin Diagram, PIC12F615/HV615 (PDIP, SOIC, TSSOP, DFN)
VDD
GP5/T1CKI/P1A*/OSC1/CLKIN
GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT
GP3/T1G*/MCLR/VPP
18
2 PIC12F615/ 7
3 HV615 6
45
VSS
GP0/AN0/CIN+/P1B/ICSPDAT
GP1/AN1/CIN0-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
* Alternate pin function.
www.DataSheet4U.comTABLE 2: PIC12F615/HV615 PIN SUMMARY (PDIP, SOIC, TSSOP, DFN)
I/O Pin Analog Comparators Timer
CCP
Interrupts Pull-ups
GP0
GP1
GP2
GP3(1)
7
6
5
4
AN0
AN1
AN2
—
CIN+
CIN0-
COUT
—
—
—
T0CKI
T1G*
P1B
—
CCP1/P1A
—
IOC
IOC
INT/IOC
IOC
Y
Y
Y
Y(2)
GP4
3
AN3
CIN1- T1G P1B*
IOC
Y
GP5
2
—
—
T1CKI
P1A*
IOC
Y
—1
—
— — — ——
—8
—
— — — ——
* Alternate pin function.
Note 1: Input only.
2: Only when pin is configured for external MCLR.
Basic
ICSPDAT
ICSPCLK/VREF
—
MCLR/VPP
OSC2/CLKOUT
OSC1/CLKIN
VDD
VSS
© 2006 Microchip Technology Inc.
Preliminary
DS41302A-page 3
5 Page 
PIC12F609/615/12HV609/615
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F609/615/12HV609/615 has a 13-bit pro-
gram counter capable of addressing an 8K x 14 pro-
gram memory space. Only the first 1K x 14 (0000h-
03FFh) for the PIC12F609/615/12HV609/615 is physi-
cally implemented. Accessing a location above these
boundaries will cause a wraparound within the first 1K
x 14 space. The Reset vector is at 0000h and the inter-
rupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1:
www.DataSheet4U.com
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F609/615/12HV609/615
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
On-chip Program
Memory
Wraps to 0000h-07FFh
0004h
0005h
03FFh
0400h
1FFFh
2.2 Data Memory Organization
The data memory (see Figure 2-2) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. Register locations F0h-FFh in Bank 1 point
to addresses 70h-7Fh in Bank 0. All other RAM is
unimplemented and returns ‘0’ when read. The RP0 bit
of the STATUS register is the bank select bit.
RP0
0 → Bank 0 is selected
1 → Bank 1 is selected
Note:
The IRP and RP1 bits of the STATUS
register are reserved and should always be
maintained as ‘0’s.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC12F609/615/12HV609/615. Each register is
accessed, either directly or indirectly, through the File
Select Register (FSR) (see Section 2.4 “Indirect
Addressing, INDF and FSR Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
© 2006 Microchip Technology Inc.
Preliminary
DS41302A-page 9
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet 12F615.PDF ] | |
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