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HY5MS7B2BLF fiches techniques PDF

Hynix - Mobile DDR SDRAM 512M

Numéro de référence HY5MS7B2BLF
Description Mobile DDR SDRAM 512M
Fabricant Hynix 
Logo Hynix 





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HY5MS7B2BLF fiche technique
512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O
Document Title
512MBit (4Bank x 4M x 32bits) MOBILE DDR SDRAM
Revision History
www.DataSheet4U.Rcoemvision No.
History
0.1 - Initial Draft
0.2 - Added SRR function and timing diagram
- Updated some AC parameters (tAC, tDQSCK, tHZ, tIS, tIH,
0.3
tIPW, tDIPW, tRFC, tXSR)
- Updated IDD5
- Corrected editorial errors in descriptions and figures
- Updated Status Register
- Rearranged pages to be more systematic
- Corrected editorial errors in descriptions and figures
0.4 - Corrected AC Input High/Low Level Voltage (VIH / VIL =
0.8*VDDQ / 0.2*VDDQ)
- Updated IDD6 current
- Updated tWTR in LPDDR333
1.0 - Reorganized and updated AC and DC Operating Conditions
- Modified Status Register Read Method
1.1 - Modified IDD4R and IDD4W
- Added DPD option
Draft Date
Sep.2006
Jan.2007
Feb. 2007
Feb. 2007
Mar. 2007
Apr. 2007
Remark
Preliminary
Preliminary
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.1 / Apr. 2007
1

PagesPages 30
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