|
|
PDF HFDOM44S3Vxxx Data sheet ( Hoja de datos )
| Número de pieza | HFDOM44S3Vxxx | |
| Descripción | 44Pin Flash Disk Module | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HFDOM44S3Vxxx (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
|
No Preview Available !
HANBit
HFDOM44S3Vxxx
44Pin Flash Disk Module Min.16MB ~ Max.384MB,
True IDE Interface
1. PRODUCT OVERVIEW
GENERAL DESCRIPTION
The HFDOM44S3Vxxx series 44Pin Flash Disk Module is a flash technology based with True IDE interface flash
memory card. It is constructed with flash disk controller chip and NAND-type (Samsung) flash memory device. The
HFDOM44S3V-xxx series operates in both 3.3-Volt and 5.0-Volt power supplies. It comes in capacity of 16, 32, 48, 64, 80,
96, 128, 144, 160, 192, 256, 272,288, 320 and up to 384MByte formatted 44Pin type .
www.DataSheet4UB.ycoomptimizing flash memory management, the life of this HFDOM44S3Vxxx series can be extended to its maximum level.
Because the ECC function is included, the correctness of data transfer between the HFDOM44S3Vxxx series and a True
IDE compatible interface device can be guaranteed.
The HFDOM44S3Vxxx series is fully compatible with applications such as CPU card / board, set top box, industry /
military PC / Notebook, security equipment, measuring instrument and embedded systems.
FEATURES
- ATA / True IDE compatible host interface
- ATA command set compatible
- Automatic sensing of PC Card ATA or true IDE host interface.
- Very high performance, very low power consumption
- Automatic error correction
- Auto Standby to save power consumption.
- Supports power down commands and sleep modes.
- Integrated PCMCIA attribute memory of 256 bytes (CIS)
- Support for 8 or 16 bit host transfers
- 3.3V/5.0V operation voltage
- Host Interface bus width : 8/16 bit Access
- Flash Interface bus width : 8 bit Access
- Capacity : Min. 16MB ~ Max. 384MB
- MTBF > 1,000,000 hours.
- Minimum 10,000 insertions.
- Shock : 2,000 G max.
- Vibration : 15 G peak to peak max.
PRODUCT SPECIFICATIONS
Capacities :
16, 32, 48, 64, 80, 96, 128, 144, 160, 192, 256, 272,288, 320 and up to 384MB (formatted)
System Compatibility :
Please refer to the compatibility list of index.
Performance :
Host Data Transfer Rates :
up to 16.6 MB/sec, PIO mode 4; 16.6MB/sec
URL:www.hbe.co.kr
Rev. 1.0 (January, 2005)
1 / 29
HANBit Electronics Co., Ltd.
1 page  
HANBit
HFDOM44S3Vxxx
Signal Descriptions
Table 2.2 Signal Descriptions
Signal Name Dir.
Pin
Description
A[2:0]
-PDIAG
-DASP
www.DataSheet4U.com
-CS0, -CS1
D[15:00]
GND
-IOR
-IOW
IRQ
-RESET
In True IDE Mode only A[2:0] are used to select the one of eight registers in
I 33,35,36 the Task File, the remaining address lines should be grounded by the host.
This input / output is the Pass Diagnostic signal in the Master / Slave
I/O 34 handshake protocol.
In the True IDE Mode, this input/output is the Disk Active/Slave
I/O 39 Present signal in the Master/Slave handshake protocol.
CS0 is the chip select for the task file registers while CS2 is used to select
I 37,38 the Alternate Status Register and the Device Control Register.
3,4,5,6,
All Task File operations occur in byte mode on the low order bus D00-D07
while all data transfers are 16 bit using D00-D15.
7,8,9,10,
I/O 11,12,13,
14,15,16,
17,18
2,19,22, Ground.
-- 24,26,
30,40,43
I 25 This is an I/O Read strobe generated by the host.
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus
into the Storage Card controller registers when the Storage Card is
I 23 configured to use the I/O interface. The clocking will occur on the negative to
positive edge of the signal (trailing edge).
O 31 In True IDE Mode signal is the active high Interrupt Request to the host.
I 1 This input pin is the active low hardware reset from the host.
IORDY
-IOIS16
VCC
O
O
Power
27
32
41,42
This output signal may be used as IORDY.
This output signal is asserted low when this device is expecting a word data
transfer cycle.
Power
URL:www.hbe.co.kr
Rev. 1.0 (January, 2005)
5 / 29
HANBit Electronics Co., Ltd.
5 Page 
HANBit
HFDOM44S3Vxxx
Bit 7: this bit is in High Imoedence..
Implementation Note:
Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller
operating at the same addresses as the CompactFlash Storage Card. Following are some
possible solutions to this problem for the PCMCIA implementation:
1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary
address (377) or in an independently decoded Address Space when a Floppy Disk Controller
is located at the Primary addresses.
2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.
3) Implement a socket adapter, which can be programmed to (conditionally) tri-state D7 of I/0
address 3F7h/377h when a Compact Flash Storage Card is installed and conversely to tri-state
D6-D0 of I/O address 3F7h/377h when a floppy controller is installed.
4) Do not use the CompactFlash Storage Card’s Drive Address register. This may be
accomplished by either a) If possible, program the host adapter to enable only I/O addresses
www.DataSheet4U.com1F0h-1F7h, 3F6h (or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided
use an additional Primary / Secondary configuration in the CompactFlash Storage Card
which does not respond to accesses to I/O locations 3F7h and 377h. With either of these
implementations, the host software must not attempt to use information in the Drive Address
Register.
Bit 6 (-WTG): this bit is 0 when a write operation is in progress, otherwise, it is 1.
Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register.
Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register.
Bit 3 (-HS1): this bit is the negation of bit 1 in the Drive/Head register.
Bit 2 (-HS0): this bit is the negation of bit 0 in the Drive/Head register.
Bit 1 (-nDS1): this bit is 0 when drive 1 is active and selected.
Bit 0 (-nDS0): this bit is 0 when the drive 0 is active and selected.
4. ATA COMMAND
CF-ATA Command Set
Table summarizes the CF-ATA command set with the paragraphs that follow describing the
individual commands and the task file for each.
Table:CF-ATA Command Set
Class
COMMAND
Code
FR SC SN CY DH
1 Check Power Mode
E5h or 98h
-
-
-
-D
1 Execute Drive Diagnostic 90h
- - - -D
2 Format Track
50h
- Y - YY
1 Identify Drive
ECh
- - - -D
1 Idle
E3h or 97h
-Y-
-D
1 Idel Immediate
E1h or 95h - - - - D
1 Initialize Drive Parameters 91h
-Y-
-Y
1 Read Buffer
E4h
- - - -D
1 Read Long Sector
22h or 23h
- - YYY
1 Read Multiple
C4h
- YYYY
1 Read Sector(s)
20h or 21h
- YYYY
1 Read Verify Sector(s) 40h or 41h
- YYYY
1 Recalibrate 1Xh - - - - D
1 Request Sence
03h
- - - -D
1 Seek
7Xh - - Y Y Y
1 Set Features
EFh
Y- - -D
LBA
-
-
Y
-
-
-
-
-
Y
Y
Y
Y
-
-
Y
-
URL:www.hbe.co.kr
Rev. 1.0 (January, 2005)
11 / 29
HANBit Electronics Co., Ltd.
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet HFDOM44S3Vxxx.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HFDOM44S3Vxxx | 44Pin Flash Disk Module | Hanbit Electronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |