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PDF HFDOM44S3Rxxx Data sheet ( Hoja de datos )
| Número de pieza | HFDOM44S3Rxxx | |
| Descripción | 44Pin Flash Disk Module | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HFDOM44S3Rxxx
44Pin Flash Disk Module Min.16MB ~ Max.512MB,
True IDE Interface
1. PRODUCT OVERVIEW
GENERAL DESCRIPTION
The HFDOM44S3Rxxx series 44Pin Flash Disk Module is a flash technology based with True IDE interface flash
memory card. It is constructed with flash disk controller chip and NAND-type (Samsung) flash memory device. The
HFDOM44S3R-xxx series operates in both 3.3-Volt and 5.0-Volt power supplies. It comes in capacity of 16, 32, 48, 64, 80,
96, 128, 144, 160, 192, 208, 224, 256, 272,288, 320, 384 and up to 512MByte formatted 44Pin type .
www.DataSheet4UB.ycoomptimizing flash memory management, the life of this HFDOM44S3Rxxx series can be extended to its maximum level.
Because the ECC function is included, the correctness of data transfer between the HFDOM44S3Rxxx series and a True
IDE compatible interface device can be guaranteed.
The HFDOM44S3Rxxx series is fully compatible with applications such as CPU card / board, set top box, industry /
military PC / Notebook, security equipment, measuring instrument and embedded systems.
FEATURES
- ATA / True IDE compatible host interface
- ATA command set compatible
- Automatic sensing of PC Card ATA or true IDE host interface.
- Very high performance, very low power consumption
- Automatic error correction
- Auto Standby to save power consumption.
- Supports power down commands and sleep modes.
- Integrated PCMCIA attribute memory of 256 bytes (CIS)
- Support for 8 or 16 bit host transfers
- 3.3V/5.0V operation voltage
- Host Interface bus width : 8/16 bit Access
- Flash Interface bus width : 8 bit Access
- Capacity : Min. 16MB ~ Max. 512MB
- MTBF > 1,000,000 hours.
- Minimum 10,000 insertions.
- Shock : 2,000 G max.
- Vibration : 15 G peak to peak max.
PRODUCT SPECIFICATIONS
Capacities :
16, 32, 48, 64, 80, 96, 128, 144, 160, 192, 208, 224, 256, 272,288, 320, 384 and up to 512MB (formatted)
System Compatibility :
Please refer to the compatibility list of index.
Performance :
Host Data Transfer Rates :
up to 16.6 MB/sec, PIO mode 4; 16.6MB/sec
URL:www.hbe.co.kr
Rev. 1.0 (January, 2005)
1 / 30
HANBit Electronics Co., Ltd.
1 page  
HANBit
HFDOM44S3Rxxx
2. PIN INFORMATION
PIN ASSIGNMENTS AND PIN TYPE
Table 2.1 Pin Assignment and Pin type
www.DataSheet4U.com
Pin
IDE
Signal
Pin Type
Pin
IDE
1 /RESET
I2
3 D07
I/O 4
5 D06
I/O 6
7 D05
I/O 8
9 D04
I/O 10
11 D03
I/O 12
13 D02
I/O 14
15 D01
I/O 16
17 D00
I/O 18
19 GND
DC 20
21 NC
-- 22
23 /IOW
I 24
25 /IOR
I 26
27 IORDY
O 28
29 NC
-- 30
31 IRQ
O 32
33 A01
I 34
35 A00
I 36
37 /CS0
I 38
39 /DASP(LED) I/O 40
41 VCC
Power
42
43
GND
Ground
44
Signal
GND
D08
D09
D10
D11
D12
D13
D14
D15
NC
GND
GND
GND
NC
GND
/IOIS16
/PDIAG
A02
/CS1
GND
VCC
NC
Pin Type
Ground
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
--
Ground
Ground
Ground
--
Ground
O
I/O
I
I
Ground
Power
--
URL:www.hbe.co.kr
Rev. 1.0 (January, 2005)
5 / 30
HANBit Electronics Co., Ltd.
5 Page 
HANBit
HFDOM44S3Rxxx
the Status register does clear a pending interrupt, while reading the Alternate Status register does not. The status
bits are described as follows:
D7
BUSY
D6
RDY
D5 D4 D3 D2
DWF
DSC
DRQ
CORR
Status & Alternate Status Register
D1
0
D0
ERR
Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the
command buffer and registers and the host is locked out from accessing the command
register and buffer. No other bits in this register are valid when this bit is set to a 1.
Bit 6 (DRDY): DRDY indicates whether the device is capable of performing CompactFlash Storage Card
www.DataSheet4U.comoperations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to
accept a command.
Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.
Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires the
information to be transferred either to or from the host through the Data register.
Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected.
This condition does not terminate a multi-sector read operation.
Bit 1 (IDX): This bit is always set to 0.
Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error
register contain additional information describing the error. It is recommended
that media access commands (such as Read Sectors and Write Sectors) that end with an
error condition should have the address of the first sector in error in the command block
registers.
9) Device Control Register( Address – 3F6h[376h]; Offset Eh)
This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to
the card. This register can be written even if the device is BUSY. The bits are defined as follows:
D& D6 D5 D4 D3 D2 D1 D0
X
X
X
X
1
SW Rst
-IEn
0
Device Control Register
Bit 7: this bit is an X (don’t care).
Bit 6: this bit is an X (don’t care).
Bit 5: this bit is an X (don’t care).
Bit 4: this bit is an X (don’t care).
Bit 3: this bit is ignored by the CompactFlash Storage Card.
Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk
controller Soft Reset operation. This does not change the PCMCIA Card
Configuration Registers (4.3.2 to 4.3.5) as a hardware Reset does. The Card remains in
Reset until this bit is reset to ‘0.’
Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1,
The interrupts from the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the
Configuration and Status Register. This bit is set to 0 at power on and Reset.
Bit 0: this bit is ignored by the CompactFlash Storage Card.
10) Card (Drive) Address Register(Address 3F7h[377h]; Offset Fh)
This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not
be mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined as follows:
D7 D6 D5 D4 D3 D2 D1 D0
URL:www.hbe.co.kr
Rev. 1.0 (January, 2005)
11 / 30
HANBit Electronics Co., Ltd.
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