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PDF HFDOM40MRxxx Data sheet ( Hoja de datos )
| Número de pieza | HFDOM40MRxxx | |
| Descripción | 40Pin Flash Disk Module | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HFDOM40MRxxx
40Pin Flash Disk Module Min.8MB ~ Max.1GB, True IDE Interface
Mode, 3.3V / 5.0V Operating
Part No. HFDOM40MRxxx
1. PRODUCT OVERVIEW
GENERAL DESCRIPTION
The HFDOM40MRxxx series 40Pin Flash Disk Module is a flash technology based with True IDE interface flash memory
card. It is constructed with flash disk controller chip and NAND-type (Samsung) flash memory device. The HFDOM40MR-
xxx series operates in both 3.3-Volt and 5.0-Volt power supplies. It comes in capacity of 16, 32, 64, 128, 192, 256, 512 MB
and up to 1GB MB formatted 40Pin type .
www.DataSheet4UB.ycoomptimizing flash memory management, the life of this HFDOM40MRxxx series can be extended to its maximum level.
Because the ECC function is included, the correctness of data transfer between the HFDOM40MRxxx series and a True
IDE compatible interface device can be guaranteed.
The HFDOM40MRxxx series is fully compatible with applications such as CPU card / board, set top box, industry /
military PC / Notebook, security equipment, measuring instrument and embedded systems.
FEATURES
- ATA / True IDE compatible host interface
- ATA command set compatible
- Automatic sensing of PC Card ATA or true IDE host interface.
- Very high performance, low power consumption
- Automatic error detection and error correction
- Auto Standby to save power consumption.
- Supports automatic power down and wake up
- Support for 8 or 16 bit host transfers
- 3.3V/5.0V operation voltage
- Host Interface bus width : 8/16 bit Access
- Flash Interface bus width : 8 bit Access
- Capacity : Min. 16MB ~ Max. 1GB
PRODUCT SPECIFICATIONS
Capacities :
16, 32, 48, 64, 96, 128, 192, 256, 512 and up to 1GB (formatted)
System Compatibility :
Please refer to the compatibility list of index.
Performance :
Host Data Transfer Rates :
up to 16.6 MB/sec, PIO mode 4; 16.6MB/sec, Multi-word
DMA mode 2; 33MB/sec
URL:www.hbe.co.kr
Rev. 1.0 (November. 2003)
1 / 1 HANBit Electronics Co., Ltd.
1 page  
HANBit
HFDOM40MRxxx
Signal Descriptions
Table 2.2 Signal Descriptions
Signal Name Dir.
Pin
Description
A[2:0]
-PDIAG
-DASP
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-CS0, -CS1
D[15:00]
GND
-IOR
-IOW
IRQ
-RESET
In True IDE Mode only A[2:0] are used to select the one of eight registers in
I 33,35,36 the Task File, the remaining address lines should be grounded by the host.
This input / output is the Pass Diagnostic signal in the Master / Slave
I/O 34 handshake protocol.
In the True IDE Mode, this input/output is the Disk Active/Slave
I/O 39 Present signal in the Master/Slave handshake protocol.
CS0 is the chip select for the task file registers while CS2 is used to select
I 37,38 the Alternate Status Register and the Device Control Register.
3,4,5,6,
All Task File operations occur in byte mode on the low order bus D00-D07
while all data transfers are 16 bit using D00-D15.
7,8,9,10,
I/O 11,12,13,
14,15,16,
17,18
2,19,22, Ground.
-- 24,26,
30,40,
I 25 This is an I/O Read strobe generated by the host.
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus
into the Storage Card controller registers when the Storage Card is
I 23 configured to use the I/O interface. The clocking will occur on the negative to
positive edge of the signal (trailing edge).
O 31 In True IDE Mode signal is the active high Interrupt Request to the host.
I 1 This input pin is the active low hardware reset from the host.
IORDY
-IOIS16
O 27 This output signal may be used as IORDY.
This output signal is asserted low when this device is expecting a word data
O 32 transfer cycle.
URL:www.hbe.co.kr
Rev. 1.0 (November. 2003)
5 / 5 HANBit Electronics Co., Ltd.
5 Page 
HANBit
HFDOM40MRxxx
Data Register
The Data Register is a 16-bit register, and it is used to transfer data blocks between the CompactFlash
Storage Card data buffer and the Host. This register overlaps the Error Register. The table below describes
the combinations of data register access and is provided to assist in understanding the overlapped Data
Register and Error/Feature Register rather than to attempt to define general PCMCIA word and byte
access modes and operations. See the PCMCIA PC Card Standard Release 2.0 for definitions of the Card
Accessing Modes for I/O and Memory cycles.
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15 14 13 12 11 10
9
8
Data (15:8)
7 6 5 4 3 2 10
Data (7:0)
Feature Register
This register provides information regarding features of the CompactFlash Storage Card that the
host can utilize. This register is also accessed on data bits D15-D8 during a write operation to
Offset 0 with -CE2 low and -CE1 high.
7 6 5 4 3 2 10
Command specific
Sector Count Register
This register contains the numbers of sectors of data requested to be transferred on a read or write
operation between the host and the CompactFlash Storage Card. If the value in this register is zero, a
count of 256 sectors is specified. If the command was successful, this register is zero at command
completion. If not successfully completed, the register contains the number of sectors that need to be
transferred in order to complete the request.
7 6 5 4 3 2 10
Sector Count
URL:www.hbe.co.kr
Rev. 1.0 (November. 2003)
11 / 11
HANBit Electronics Co., Ltd.
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