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PDF 8250ACZUMHB Data sheet ( Hoja de datos )
| Número de pieza | 8250ACZUMHB | |
| Descripción | KMPC8250ACZUMHB | |
| Fabricantes | Motorola Semiconductor | |
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Technical Data
MPC8250EC/D
Rev. 0.9 8/2003
MPC8250
Hardware Specifications
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This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC8250 PowerQUICC II™
communications processor.
The following topics are addressed:
Topic
Page
Section 1.1, “Features”
2
Section 1.2, “Electrical and Thermal Characteristics”
5
Section 1.2.1, “DC Electrical Characteristics”
5
Section 1.2.2, “Thermal Characteristics”
10
Section 1.2.3, “Power Considerations”
10
Section 1.2.4, “AC Electrical Characteristics”
11
Section 1.3, “Clock Configuration Modes”
19
Section 1.3.1, “Local Bus Mode”
19
Section 1.3.2, “PCI Mode”
22
Section 1.4, “Pinout”
28
Section 1.5, “Package Description”
53
Section 1.6, “Ordering Information”
56
The MPC8250 is available in two packages—the standard ZU package (480 TBGA) and an
alternate VR package (516 PBGA)—as described in Section 1.4, “Pinout,” and Section 1.5,
“Package Description.” For more information on VR packages, contact your Motorola sales
office. Note that throughout this document references to the MPC8250 are inclusive of its VR
version unless otherwise specified.
NOTE: Document Revision History
Changes to this document are summarized in Table 23 on
page 56.
1 page  
Electrical and Thermal Characteristics
•
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– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
PCI bridge
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Peripheral capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8265A) required by the PCI standard as well as message and
doorbell registers
— Supports the I2O standard
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specification
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
1.2 Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8250.
1.2.1 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MPC8250. Table 1 shows the maximum
electrical ratings.
MOTOROLA
MPC8250 Hardware Specifications
5
5 Page 
Electrical and Thermal Characteristics
1.2.3.1 Layout Practices
Each VCC pin should be provided with a low-impedance path to the board’s power supply. Each ground pin
should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct
groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 µF
by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an inch
per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes.
All output pins on the MPC8250 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
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bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs
during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required for conditions above PD = 3W (when the ambient temperature is 70˚ C or
greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that the
I/O power should be included when determining whether to use a heat sink.
Table 5. Estimated Power Dissipation for Various Configurations1
Bus CPM Core CPU CPM
(MHz) Multiplier Multiplier (MHz)
CPU
(MHz)
PINT(W)2
Vddl 1.8 Volts
Vddl 2.0 Volts
Nominal Maximum Nominal Maximum
66.66
2
3 133 200 1.2 2 1.8 2.3
66.66
2.5
3
166 200 1.3 2.1 1.9 2.3
66.66
3
4 200
66.66
3
4.5 200
83.33
2
3 166
83.33
2
3 166
83.33
2.5
3.5
208
1 Test temperature = room temperature (25˚ C)
2 PINT = IDD x VDD Watts
266
300
250
250
291
—
—
—
—
—
— 2.3 2.9
— 2.4 3.1
— 2.2 2.8
— 2.2 2.8
— 2.4 3.1
1.2.4 AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC8250 device. Note that AC timings are based on a 50-pf load. Typical output
buffer impedances are shown in Table 6.
MOTOROLA
MPC8250 Hardware Specifications
11
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