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PDF ICS840024I Data sheet ( Hoja de datos )
| Número de pieza | ICS840024I | |
| Descripción | CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840024I
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS840024I is a 4 output LVCMOS/LVTTL
ICS Synthesizer optimized to generate Ethernet
HiPerClockS™ reference clock frequency and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. The ICS840024I uses ICS’ 3rd
generation low phase noise VCO technology and can achieve
1ps or lower typical random rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS840024I is packaged in a
www.DataSheest4mUa.cllo2m0-pin TSSOP package.
FEATURES
• Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following output frequency: 125MHz
• RMS phase jitter @125MHz (1.875MHz - 20MHz):
0.60ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
OE Pullup
nPLL_SEL Pulldown
nXTAL_SEL Pulldown
XTAL_IN 25MHz
OSC 0
XTAL_OUT
TEST_CLK Pulldown
1
Phase
Detector
VCO
1
0
M = ÷25 (fixed)
Pulldown
MR
÷5
PIN ASSIGNMENT
nc 1 20 nc
nc 2 19 GND
nXTAL_SEL 3 18 Q0
TEST_CLK 4 17 Q1
OE 5
1 6 VDDO
MR 6 15 Q2
nPLL_SEL 7 14 Q3
Q0
VDDA 8
13 GND
nc 9 12 XTAL_IN
VDD 10 11 XTAL_OUT
Q1
ICS840024I
Q2 20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
Q3 package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840024AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 16, 2004
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840024I
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
tsk(o)
Output Frequency
Output Skew; NOTE 1, 3
125
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
Intergration Range
1.875MHz - 20MHz
0.60
tL
www.DataSheet4tRU./ctoFm
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
400
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
MHz
ps
ps
ms
ps
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
fOUT
tsk(o)
Output Frequency
Output Skew; NOTE 1, 3
125
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
Intergration Range
1.875MHz - 20MHz
0.55
t
L
tR / tF
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
400
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
Units
MHz
ps
ps
ms
ps
%
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
tsk(o)
Output Frequency
Output Skew; NOTE 1, 3
125
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
Intergration Range
1.875MHz - 20MHz
0.50
tL
tR / tF
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
400
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
MHz
ps
ps
ms
ps
%
840024AGI
www.icst.com/products/hiperclocks.html
5
REV. A DECEMBER 16, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840024I
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
www.DataSheet4U.com
840024AGI
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MIN MAX
N 20
A -- 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 6.40 6.60
E 6.40 BASIC
E1 4.30 4.50
e 0.65 BASIC
L 0.45 0.75
α 0° 8°
aaa -- 0.10
Reference Document: JEDEC Publication 95, MO-153
www.icst.com/products/hiperclocks.html
11
REV. A DECEMBER 16, 2004
11 Page | ||
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| PDF Descargar | [ Datasheet ICS840024I.PDF ] | |
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