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PDF ICS840008-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS840008-01 | |
| Descripción | CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS840008-01 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840008-01
FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS840008-01 is an 8 output LVCMOS/LVTTL
ICS Synthesizer designed to generate 125MHz for
HiPerClockS™ Gigabit Ethernet applications and is a member of
the HiPerClocksTM family of high performance clock
solutions from ICS. The ICS840008-01 uses ICS’
3rd generation low phase noise VCO technology and can achieve
1ps or lower typical random rms phase jitter, easily meeting
Gigabit Ethernet jitter requirements. The ICS840008-01 is
www.DataSheept4aUc.kcaomged in a small 24-pin SSOP package.
FEATURES
• Eight LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Output frequency range: 125MHz - 160MHz
• Crystal oscillator interface, 25MHz - 32MHz crystal
• VCO range: 500MHz - 640MHz
• RMS phase jitter (1.875MHz - 20MHz): 0.52ps (typical)
• Output skew: 150ps (maximum) (design target)
• Voltages supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
nPLL_SEL Pulldown
XTAL_IN
XTAL_OUT
25MHz
OSC
Phase
Detector
1
VCO
500MHz -
640MHz
0
MR Pulldown
OE Pullup
÷20 (fixed)
PIN ASSIGNMENT
÷4 (fixed)
8
8
Q0:Q7
VDDO
nc
XTAL_OUT
XTAL_IN
VDDA
OE
MR
nPLL_SEL
VDD
nc
GND
nc
1
2
3
4
5
6
7
8
9
10
11
12
24 Q0
23 Q1
22 GND
21 Q2
20 Q3
1 9 VDDO
18 Q4
17 Q5
16 GND
15 Q6
14 Q7
1 3 VDDO
ICS840008-01
24-Lead SSOP, 150MIL
3.9mm x 8.65mm x 1.5mm
package body
R Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840008AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840008-01
FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±10%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
tsk(o)
Output Frequency
Output Skew; NOTE 1, 3
125
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
Integration Range:
1.875MHz - 20MHz
0.52
tL
www.DataSheet4tRU/.ctoFm
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
550
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
160
MHz
ps
ps
ms
ps
%
TABLE
5B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
3.3V±10%,
V
DDO
=
2.5V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical
fOUT
tsk(o)
Output Frequency
Output Skew; NOTE 1, 3
125
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
Integration Range:
1.875MHz - 20MHz
0.53
tL
tR / tF
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
600
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
160
Units
MHz
ps
ps
ms
ps
%
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, VDDO = 1.8V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
fOUT
tsk(o)
Output Frequency
Output Skew; NOTE 1, 3
125
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
Integration Range:
1.875MHz - 20MHz
0.49
tL
tR / tF
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
630
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
160
Units
MHz
ps
ps
ms
ps
%
840008AR-01
www.icst.com/products/hiperclocks.html
5
REV. A APRIL 7, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840008-01
FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SSOP
www.DataSheet4U.com
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
73.1°C/W
1
65.9°C/W
2.5
60.5°C/W
TRANSISTOR COUNT
The transistor count for ICS840008-01 is: 3378
840008AR-01
www.icst.com/products/hiperclocks.html
11
REV. A APRIL 7, 2005
11 Page | ||
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