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National Semiconductor - Serializer

Numéro de référence DS32EL0421
Description Serializer
Fabricant National Semiconductor 
Logo National Semiconductor 





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DS32EL0421 fiche technique
PRELIMINARY
May 9, 2008
DS32EL0421, DS32ELX0421
125 – 312.5 MHz Serializer with DDR LVDS Parallel LVDS
Interface
General Description
The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz
(DDR) serializer for high-speed serial transmission over FR-4
printed circuit board backplanes, balanced cables, and optical
fiber. This easy-to-use chipset integrates advanced signal
and clock conditioning functions, with an FPGA friendly inter-
www.DataSheefta4cUe..com
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel
input LVDS channels to create a maximum data payload of
3.125 Gbps. If the integrated DC-balance encoding is en-
abled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote
sense capability to automatically detect and negotiate link
status with its companion DS32EL0124/DS32ELX0124 de-
serializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board
trace count and alleviates EMI issues, when compared to tra-
ditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through
a SMBus interface as well as through control pins.
Target Applications
Imaging: Industrial, Medical Security, Printers
Displays: LED walls, Commercial
Video Transport
Communication Systems
Test and Measurement
Industrial Bus
Features
5-bit LVDS parallel data interface
Programmable transmit de-emphasis
Configurable output levels (VOD)
Selectable DC-balanced encoder
Selectable data scrambler
Remote Sense for automatic detection and negotiation of
link status
On chip LC VCOs
Redundant serial output (ELX device only)
Data valid signaling to assist with synchronization of
multiple receivers
Supports AC- and DC-coupled signaling
Integrated CML and LVDS terminations
Configurable PLL loop bandwidth
Programmable output termination (50or 75Ω).
Built-in test pattern generator
Loss of lock and error reporting
Configurable via SMBus
48-pin LLP package with exposed DAP
Key Specifications
1.25 to 3.125 Gbps serial data rate
125 to 312.5 MHz DDR parallel clock
-40° to +85°C temperature range
>8 kV ESD (HBM) protection
Low Intrinsic Jitter — 35ps at 3.125 Gbps
Typical Application
© 2008 National Semiconductor Corporation 300321
30032101
www.national.com

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