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PDF UT7Q512 Data sheet ( Hoja de datos )
| Número de pieza | UT7Q512 | |
| Descripción | 512K x 8 SRAM | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
QCOTSTM UT7Q512 512K x 8 SRAM
Data Sheet
August, 2002
FEATURES
q 100ns (5 volt supply) maximum address access time
q Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
q TTL compatible inputs and output levels, three-state
www.DataSheet4U.cboimdirectional data bus
q Typical radiation performance
- Total dose: 30krad(Si)
- 30krad(Si) to 300krad(Si), depending on orbit, using
Aeroflex UTMC patented shielded package
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = 5MeV-cm 2/mg
- Saturated Cross Section (cm2) per bit, ~1.0E-7
- 1.5E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
q Packaging options:
- 32-lead ceramic flatpack (weight 2.5-2.6 grams)
q Standard Microcircuit Drawing 5962-99606
- QML T and Q compliant
INTRODUCTION
The QCOTSTM UT7Q512 Quantified Commercial Off-the-
Shelf product is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E),
an active LOW Output Enable (G), and three-state drivers.
This device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the device is accomplished by taking the Chip
Enable One ( E) input LOW and the Write Enable ( W) input
LOW. Data on the eight I/O pins (DQ0 through DQ7) is then
written into the location specified on the address pins (A0
through A18). Reading from the device is accomplished by
taking Chip Enable One (E) and Output Enable (G) LOW
while forcing Write Enable (W) HIGH. Under these
conditions, the contents of the memory location specified
by the address pins will appear on the eight I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed
in a high impedance state when the device is deselected (E,
HIGH), the outputs are disabled (G HIGH), or during a write
operation (E LOW and W LOW).
Clk. Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DQ0 -DQ 7
Data
Control
CLK
Gen.
Memory Array
1024 Rows
512x8 Columns
I/O Circuit
Column Select
E
W
G
Figure 1. UT7Q512 SRAM Block Diagram
1 page  
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(VDD = 5.0V±10%) (-55°C to +125°C)
SYMBOL
PARAMETER
CONDITION
MIN
VIH High-level input voltage
VIL Low-level input voltage
2.2
VOL
VOH
CIN1
www.DataSheet4UC.cIoOm1
IIN
IO Z
IOS2, 3
IDD(OP)
Low-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
Short-circuit output current
Supply current operating
@ 1MHz
IOL = 2.1mA,VDD =4.5V
IOH = -1mA,VDD =4.5V
ƒ = 1MHz @ 0V
ƒ = 1MHz @ 0V
VSS < VIN < VDD , VDD = VDD (max)
0V < VO < VDD
VDD = VDD (max)
G = VDD (max)
0V <VO <VDD
Inputs: VIL = VSS + 0.8V,
VIH = 2.2V
IOUT = 0mA
VDD = VDD (max)
2.4
-2
-2
-80
IDD1(OP) Supply current operating
@10MHz
IDD2(SB) Nominal standby supply current
@0MHz
Inputs: VIL = VSS + 0.8V,
VIH = 2.2V
IOUT = 0mA
VDD = VDD (max)
Inputs: VIL = VSS
IOUT = 0mA
E = VDD - 0.5
VDD = VDD (max)
VIH = VDD - 0.5V
-55°C and
25°C
+125°C
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 .
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
MAX
.8
0.4
10
10
2
2
UNIT
V
V
V
V
pF
pF
µA
µA
80 mA
50 mA
100 mA
35 µA
1 mA
5
5 Page 
DATA RETENTION MODE
VDD
50%
tEFR
VDR > 4.5V
50%
tR
E
www.DataSheet4U.com
Figure 7. Low VDD Data Retention Waveform (100ns)
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(TC = 25°C, 1 Sec Data Retention Test)
SYMBOL
PARAMETER
VDR
IDDR 1
tEFR 1,2
tR1 , 2
VDD for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Notes:
1. E = VSS, all other inputs = VDR or VSS.
2. Not guaranteed or tested.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(TC = 25°C, 10 Second Data Retention Test)
SYMBOL
PARAMETER
V DD 1
VDD for data retention
tEFR2, 3
Chip select to data retention time
tR2, 3
Operation recovery time
Notes:
1. Performed at VDD (min) and VDD (max).
2. E = VSS, all other inputs = VDR or VSS.
3. Not guaranteed or tested.
MINIMUM
4.5
--
0
tAVAV
MAXIMUM
--
.4
UNIT
V
mA
ns
ns
MINIMUM
4.5
0
tAVAV
MAXIMUM UNIT
5.5 V
ns
ns
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UT7Q512.PDF ] | |
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