IDT72041 Datasheet PDF - Integrated Device Technology
| Part Number | IDT72041 | |
| Description | (IDT720x1) CMOS ASYNCHRONOUS FIFO | |
| Manufacturers | Integrated Device Technology | |
| Logo |  |
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Integrated Device Technology, Inc.
CMOS ASYNCHRONOUS FIFO WITH
RETRANSMIT
1K x 9, 2K x 9, 4K x 9
IDT72021
IDT72031
IDT72041
FEATURES:
• First-In/First-Out Dual-Port memory
• Bit organization
– IDT72021—1K x 9
– IDT72031—2K x 9
– IDT72041—4K x 9
• Ultra high speed
– IDT72021—25ns access time
– IDT72031—35ns access time
www.DataShe–et4UID.cTom72041—35ns access time
• Easily expandable in word depth and/or width
• Asynchronous and simultaneous read and write
• Functionally equivalent to IDT7202/03/04 with Output
Enable (OE ) and Almost Empty/Almost Full Flag (AEF )
• Four status flags: Full, Empty, Half-Full (single device
mode), and Almost Empty/Almost Full (7/8 empty or 7/8
full in single device mode)
• Output Enable controls the data output port
• Auto-retransmit capability
• Available in 32-pin DIP and PLCC
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40oC to +85oC) is avail
able, tested to military electrical specifications
DESCRIPTION:
IDT72021/031/041s are high-speed, low-power, dual-port
memory devices commonly known as FIFOs (First-In/First-
Out). Data can be written into and read from the memory at
independent rates. The order of information stored and ex-
tracted does not change, but the rate of data entering the FIFO
might be different than the rate leaving the FIFO. Unlike a
Static RAM, no address information is required because the
read and write pointers advance sequentially. The IDT72021/
031/041s can perform asynchronous and simultaneous read
and write operations. There are four status flags, (HF , FF , EF ,
AEF ) to monitor data overflow and underflow. Output Enable
(OE ) is provided to control the flow of data through the output
port. Additional key features are Write (W ), Read (R ), Retrans-
mit (RT ), First Load (FL ), Expansion In (XI ) and Expansion Out
(XO ). The IDT72021/031/041s are designed for those appli-
cations requiring data control flags and Output Enable (OE ) in
multiprocessing and rate buffer applications.
The IDT72021/031/041s are fabricated using IDT’s CMOS
technology. Military grade product is manufactured in compli-
ance with the latest version of MIL-STD-883, Class B, for high
reliability systems.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUT
(D0–D8)
W
WRITE
CONTROL
WRITE
POINTER
1
2
RAM
ARRAY
1024 x 9
2048 x 9
4096 x 9
1024/
2048/
4096
READ
POINTER
OE
THREE-
STATE
BUFFERS
RESET
LOGIC
RS
FL/RT
R
READ
CONTROL
DATA OUTPUTS
(Q0–Q8)
FLAG
LOGIC
EXPANSION
XI LOGIC
EF
FF
AEF
XO/HF
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
2677 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.09
DECEMBER 1996
DSC-2677/7
1
|
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IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS — IDT72021(1)
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5V±10%, TA = –55°C to +125°C)
Com’l
Mil.
Com’l
Mil. Com’l & Mil.
72021L25 72021L30 72021L35 72021L40 72021L50
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Shift Frequency
— 28.5 — 25 — 22.2 — 20 — 15 MHz
tRC R Cycle Time
35 — 40 — 45 — 50 — 65 — ns
tA Access Time
— 25 — 30 — 35 — 40 — 50 ns
tRR R Recovery Time
10 — 10 — 10 — 10 — 15 — ns
tRPW
R Pulse Width(2)
25 — 30 — 35 — 40 — 50 — ns
tRLZ R Pulse LOW to Data Bus at Low-Z(3) 5 — 5 — 5 — 5 — 10 — ns
tWLZ W Pulse HIGH to Data Bus at Low-Z(3,4) 5 — 5 — 5 — 5 — 5 — ns
www.DataShetDeVt4U.com Data Valid from R Pulse HIGH
5 — 5 — 5 — 5 — 5 — ns
tRHZ R Pulse HIGH to Data Bus at High-Z(3) — 18 — 20 — 20 — 25 — 30 ns
tWC
tWPW
W Cycle Time
W Pulse Width(2)
35 — 40 — 45 — 50 — 65 — ns
25 — 30 — 35 — 40 — 50 — ns
tWR W Recovery Time
10 — 10 — 10 — 10 — 15 — ns
tDS Data Set-up Time
15 — 18 — 18 — 20 — 30 — ns
tDH Data Hold Time
0 — 0 — 0 — 0 — 5 — ns
tRSC
tRS
RS Cycle Time
RS Pulse Width(2)
35 — 40 — 45 — 50 — 65 — ns
25 — 30 — 35 — 40 — 50 — ns
tRSS RS Set-up Time
25 — 30 — 35 — 40 — 50 — ns
tRSR
tRTC
tRT
RS Recovery Time
RT Cycle Time
RT Pulse Width(2)
10 — 10 — 10 — 10 — 15 — ns
35 — 40 — 45 — 50 — 65 — ns
25 — 30 — 35 — 40 — 50 — ns
tRTR RT Recovery Time
10 — 10 — 10 — 10 — 15 — ns
tRSF1
tRSF2
tREF
RS to EF and AEF LOW
RS to HF and FF HIGH
R LOW to EF LOW
— 35 — 40 — 45 — 50 — 65 ns
— 35 — 40 — 45 — 50 — 65 ns
— 25 — 30 — 30 — 35 — 45 ns
tRFF R HIGH to FF HIGH
— 25 — 30 — 30 — 35 — 45 ns
tRPE
tWEF
R Pulse Width After EF HIGH
W HIGH to EF HIGH
25 — 30 — 35 — 40 — 50 — ns
— 25 — 30 — 30 — 35 — 45 ns
tWFF
W LOW to EF LOW
— 25 — 30 — 30 — 35 — 45 ns
tWHF
W LOW to HF LOW
— 35 — 40 — 45 — 50 — 65 ns
tRHF R HIGH to HF HIGH
— 35 — 40 — 45 — 50 — 65 ns
tWPF
W Pulse Width after FF HIGH
25 — 30 — 35 — 40 — 50 — ns
tRF R HIGH to Transitioning AEF
— 35 — 40 — 45 — 50 — 65 ns
tWF
tOEHZ
tOELZ
W LOW to Transitioning AEF
OE HIGH to High-Z (Disable)(3)
OE LOW to Low-Z (Enable)(3)
— 35 — 40 — 45 — 50 — 65 ns
0 12 0 15 0 17 0 20 0 25 ns
0 12 0 15 0 17 0 20 0 25 ns
tAOE
OE LOW Data Valid (Q0–Q8)
— 15 — 18 — 20 — 25 — 30 ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
2677 tbl 08
5.09 5
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| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IDT72041.PDF Datasheet ] | |
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