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PDF P4C1023 Data sheet ( Hoja de datos )
| Número de pieza | P4C1023 | |
| Descripción | LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM | |
| Fabricantes | Pyramid Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de P4C1023 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
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P4C1023/P4C1023L
LOW POWER 128K x 8
SINGLE CHIP ENABLE
CMOS STATIC RAM
FEATURES
VCC Current
— Operating: 35mA
— CMOS Standby: 100µA
Access Times
—55/70 ns
Single 5 Volts ±10% Power Supply
www.DataSheet4UE.caomsy Memory Expansion Using CE and OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 400 or 600 mil Ceramic DIP
—32-Pin Ceramic SOJ
DESCRIPTION
The P4C1023L is a 1 Megabit low power CMOS static
RAM organized as 128K x 8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1023L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Read-
ing is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either CE is HIGH or
WE is LOW.
The P4C1023L is packaged in a 32-pin 400 or 600 mil
ceramic DIP and in a 32-pin ceramic SOJ.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (C10, C11), CERAMIC SOJ (CJ1)
TOP VIEW
Document # SRAM126 REV OR
Revised October 2005
1
1 page  
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
-55
Min Max
tWC Write Cycle Time
55
tCW
Chip Enable Time
to End of Write
50
tAW
Address Valid to
End of Write
50
tAS Address Set-up Time
0
www.DataSheet4U.cotmWP
Write Pulse Width
40
tAH Address Hold Time
0
tDW
Data Valid to End
of Write
tDH Data Hold Time
tWZ
Write Enable to
Output in High Z
tOW
Output Active from
End of Write
25
0
25
5
WRITE CYCLE NO. 1 (WE CONTROLLED)(6)
P4C1023/P4C1023L
-70
Min Max
70
60
60
0
50
0
30
0
30
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
6. CE and WE are LOW for WRITE cycle.
7. OE is LOW for this WRITE cycle to show twz and tow.
8. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM126 REV OR
Page 5 of 11
5 Page 
P4C1023/P4C1023L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
REV.
OR
ISSUE
DATE
Oct-05
SRAM126
P4C1023 / P4C1023L LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC
RAM
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
JDB New Data Sheet
www.DataSheet4U.com
Document # SRAM126 REV OR
Page 11 of 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet P4C1023.PDF ] | |
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