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PDF HX6256 Data sheet ( Hoja de datos )
| Número de pieza | HX6256 | |
| Descripción | 32K x 8 Static RAM | |
| Fabricantes | Honeywell | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HX6256 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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HX6256
32K x 8 Static RAM
The 32K x 8 Radiation Hardened Static RAM is a high performance 32,768
word x 8-bit static random access memory with industry-standard
functionality. It is fabricated with Honeywell’s radiation hardened
technology, and is designed for use in systems operating in radiation
environments. The RAM operates over the full military temperature range
and requires only a single 5 V ± 10% power supply. The RAM is available
www.DatawShitehet4eUit.hceomr TTL or CMOS compatible I/O. Power consumption is typically
less than 15 mW/MHz in operation, and less than 5 mW when de-selected.
The RAM read operation is fully asynchronous, with an associated typical
access time of 17 ns at 5 V.
Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensitive CMOS)
technology is radiation hardened through the use of advanced and
proprietary design, layout, and process hardening techniques. The
RICMOS™ IV process is a 5-volt, SOI CMOS technology with a 150 Å gate oxide and a minimum drawn feature size of
0.75 µm (0.6 µm effective gate length—Leff). Additional features include tungsten via plugs, Honeywell’s proprietary
SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability. A 7
transistor (7T) memory cell is used for superior single event upset hardening, while three layer metal power bussing and
the low collection volume SOI substrate provide improved dose rate hardening.
FEATURES
RADIATION
• Fabricated with RICMOS™ IV Silicon on Insulator
(SOI) 0.7 µm Process (Leff = 0.6 µm)
• Total Dose Hardness through 1x106 rad(SiO2)
• Neutron Hardness through 1x1014 cm-2
• Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
• Dose Rate Survivability through 1x1011 rad(Si)/s
• Soft Error Rate of <1x10-10 upsets/bit-day in
Geosynchronous Orbit
• No Latchup
OTHER
• Listed On SMD#5962–95845
• Fast Cycle Times
o ≤ 17 ns (Typical)
o ≤ 25 ns (-55 to 125°C) Read Write Cycle
• Asynchronous Operation
o CMOS or TTL Compatible I/O
• Single 5 V ± 10% Power Supply
• Packaging Options
o 28-Lead CFP (0.500 in. x 0.720 in.)
o 28-Lead DIP, MIL-STD-1835, CDIP2-T28
o 36-Lead CFP—Bottom Braze (0.630 x 0.650 in.)
o 36-Lead CFP—Top Braze (0.630 x 0.650 in.)
1 page  
HX6256
DC ELECTRICAL CHARACTERISTICS
Symbol
IDDSB1
Parameter
Static Supply Current
IDDSBMF
IDDOPW
IDDOPR
Standby Supply Current –
Deselected
Dynamic Supply Current –
Selected (Write)
Dynamic Supply Current –
Selected (Read)
Typical
(1)
0.2
0.2
3.4
2.8
Worst Case (2)
Min Max
1.5
1.5
4.0
4.0
Units
Test Conditions
mA
VIH=VDD, IO=0
VIL=VSS, f=0MHz
mA
NCS=VDD, IO=0,
f=40 MHZ
mA
F=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
mA
F=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
www.DataSIhIeet4U.com Input Leakage Current
-5 +5 µA VSS ≤ VI ≤ VDD
IOZ Output Leakage Current
-10
+10
µA
VSS ≤ VI ≤ VDD
Output = high Z
VIL
Low-Level Input Voltage CMOS
TTL
1.7
0.3xVDD
0.8
V
March Pattern
VDD = 4.5V
VIH
High-Level Input Voltage CMOS 3.2 0.7xVDD
TTL 2.2
V
March Pattern
VDD = 4.5V
VOL
Low-Level Output Voltage
0.3
0.05
0.4
0.05
VDD=4.5V, IOL = 10 mA (CMOS)
V = 8 mA (TTL) VDD=4.5V, IOL = 200
µA
VOH
High-Level Output Voltage
4.3
4.5
4.2
VDD-
0.05
V
VDD=4.5V, IOH=-5mA
VDD=4.5V, IOH=-200 µA
(1) Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
www.honeywell.com/radhard
5
5 Page 
HX6256
PACKAGING
The 32K x 8 SRAM is offered in two custom 36-lead flat
packs, a 28-Lead FP, or standard 28-lead DIP. Each
package is constructed of multilayer ceramic (Al2O3) and
features internal power and ground planes. The 36-lead
flat packs also feature a non-conductive ceramic tie bar
on the lead frame. The tie bar allows electrical testing of
the device, while preserving the lead integrity during
shipping and handling, up to the point of lead forming
and insertion.
28-LEAD DIP & FP PINOUT
www.DataSheet4U.com
On the bottom brazed 36-lead FP, ceramic chip
capacitors can be mounted to the package by the user to
maximize supply noise decoupling and increase board
packing density. These capacitors connect to the internal
package power and ground planes. This design
minimizes resistance and inductance of the bond wire
and package. All NC (no connect) pins must be
connected to either VDD, VSS or an active driver to
prevent charge build up in the radiation environment.
36-LEAD FP PINOUT
28-LEAD FLAT PACK (22017842-001)
All dimensions in inches
A 0.105 ± 0.015
b 0.017 ± 0.002
C 0.003 to 0.006
D 0.720 ± 0.008
e 0.050 ± 0.005 [1]
E 0.500 ± 0.007
E2 0.380 ± 0.008
E3 0.060 ref
F 0.650 ± 0.005 [2]
G 0.035 ± 0.004
L 0.295 min [3]
Q 0.026 to 0.045
S 0.045 ± 0.010
U 0.130 ref
W 0.050 ref
X 0.075 ref
Y 0.010 ref
[1] BSC – Basic lead spacing between centers
[2] Where lead is brazed to package
[3] Parts delivered with leads unformed
[4] Lid connected to VSS
28-LEAD DIP (22017785-001)
For 28-Lead DIP description, see MIL-STD-1835, Type CDIP2-T28, Config. C, Dimensions D-10
www.honeywell.com/radhard
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HX6256.PDF ] | |
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