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PDF EDI8F81024C Data sheet ( Hoja de datos )
| Número de pieza | EDI8F81024C | |
| Descripción | 1Mx8 Static RAM CMOS | |
| Fabricantes | White Electronic Designs Corporation | |
| Logotipo |  |
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White Electronic Designs
EDI8F81024C
1Mx8 Static RAM CMOS, Module
FEATURES
1024Kx8 bit CMOS Static
Random Access Memory
www.DataSheet4U.com • Access Times 70 thru 100ns
• Data Retention Function (EDI8F81024LP)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
High Density Packaging
• 36 Pin SIP, No. 62
Single +5V (±10%) Supply Operation
*This product is subject to change without notice.
DESCRIPTION
The EDI8F81024C is a 8Mb CMOS Static RAM based on eight
128Kx8 Static RAMs mounted on a multi-layered epoxy laminate
(FR4) substrate.
A version featuring Low Power with Data Retention (EDI8F81024LP)
is also available.
The EDI8F81024C is offered in a double sided, 36 pin single-in-line
Package (SIP). Surface mount SIP technology is a cost effective
solution to very high packing density requirements.
All inputs and outputs are TTL compatible and operate from a single
5V supply. Fully asynchronous, the EDI8F81024C requires no clocks
or refreshing for operation.
PIN CONFIGURATIONS AND BLOCK DIAGRAM
NC 1
VCC 2
W# 3
DQ2 4
DQ3 5
DQ0 6
A1 7
A2 8
A3 9
A4 10
VSS
DQ5
11
12
A10 13
A11 14
A5 15
A13 16
A14 17
A19 18
E# 19
A15 20
A16 21
A12 22
A18 23
A6 24
DQ1 25
VSS 26
A0 27
A7 28
A8 29
A9 30
DQ7 31
DQ4 32
DQ6 33
A17 34
VCC 35
G# 36
PIN OUT
A0-A16
W#
G#
PIN NAMES
AØ-A19
E#
W#
G#
DQØ-DQ7
VCC
VSS
NC
Address Inputs
Chip Enable
Write Enable
Output Enable
Common Data Input/Output
Power (+5V±10%)
Ground
No Connection
A19
A18
A17
DEC
E#
128K
X8
128K
X8
128K
X8
128K
X8
128K
X8
128K
X8
128K
X8
128K
X8
DQ0-DQ7
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 8
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
EDI8F81024C
WRITE CYCLE 2 - E# CONTROLLED
TAVAV
www.DataSheet4U.com
A
E#
W#
D
Q
TAVEL
TELEH
TAVEH
TWLEH
TEHAX
HIGH Z
TDVEH
TEHDX
DATA VALID
Characteristic
Data Retention Voltage
Data Retention Quiescent Current
Sym Test Conditions VCC Min Typ
Max Unit
70°C 85°C
VCC VCC = 0.2V
2
–
––
V
ICCDR
E# ≥ VCC -0.2V
2V
–
25
300 400
µA
VIN ≥ VCC -0.2V
3V
–
50
450 550
µA
Chip Disable to Data Retention Time (1) TCDR or VIN ≤ 0.2V
0 – – – ns
Operation Recovery Time (1)
TR
TAVAV*
–
– – ns
Note 1: Parameter guaranteed, but not tested.
* Read Cycle Time
DATA RETENTION E# CONTROLLED
VCC
DATA RETENTION MODE
4.5V
VCC
4.5V
TCDR
E#≥VDD-0.2V
E#
TR
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 8
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet EDI8F81024C.PDF ] | |
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