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PDF 45116 Data sheet ( Hoja de datos )
| Número de pieza | 45116 | |
| Descripción | HSP45116 | |
| Fabricantes | Intersil Corporation | |
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TM
Data Sheet
May 1999
HSP45116
FN2485.7
Numerically Controlled
Oscillator/Modulator
The Intersil HSP45116 combines a high performance
quadrature Numerically Controlled Oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a
complex vector to be multiplied by the internally generated
(cos, sin) vector for quadrature modulation and
demodulation. As shown in the Block Diagram, the
www.DataSheHeSt4PU4.c5o1m16 is divided into three main sections. The
Phase/Frequency Control Section (PFCS) and the
Sine/Cosine Section together form a complex NCO. The
CMAC multiplies the output of the Sine/ Cosine Section with
an external complex vector.
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.008Hz at 33MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector
and can accumulate the result. The resulting complex vectors
are available through two 20-bit output ports which maintain
the 90dB spectral purity. This result can be accumulated
internally to implement an accumulate and dump filter.
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be down converted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.
Features
• NCO and CMAC on One Chip
• 15MHz, 25.6MHz, 33MHz Versions
• 32-Bit Frequency Control
• 16-Bit Phase Modulation
• 16-Bit CMAC
• 0.008Hz Tuning Resolution at 33MHz
• Spurious Frequency Components < -90dBc
• Fully Static CMOS
Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL
• Phase Shifter
• Polar to Cartesian Conversions
Ordering Information
TEMP.
PART NUMBER RANGE (oC) PACKAGE
PKG. NO.
HSP45116VC-15
0 to 70 160 Ld MQFP Q160.28x28
HSP45116VC-25
0 to 70 160 Ld MQFP Q160.28x28
HSP45116GC-15
0 to 70 145 Ld CPGA G145.A
HSP45116GC-25
0 to 70 145 Ld CPGA G145.A
HSP45116GC-33
0 to 70 145 Ld CPGA G145.A
HSP45116GI-15
-40 to 85 145 Ld CPGA G145.A
HSP45116GI-25
-40 to 85 145 Ld CPGA G145.A
HSP45116GI-33
-40 to 85 145 Ld CPGA G145.A
HSP45116GM-15/883 -55 to 125 145 Ld CPGA G145.A
HSP45116GM-25/883 -55 to 125 145 Ld CPGA G145.A
HSP45116AVC-52
0 to 70 160 Ld MQFP Q160.28x28
† This part has its own data sheet under HSP45116A,
Document # FN4156.
Block Diagram
MICROPROCESSOR
INTERFACE
INDIVIDUAL
CONTROL SIGNALS
1
PHASE/
FREQUENCY
CONTROL
SECTION
SINE/
COSINE
ARGUMENT
SINE/
COSINE
SECTION
VECTOR INPUT
RI
SIN
COS
CMAC
RI
VECTOR OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1 page  
HSP45116
Pin Description
NAME
VCC
GND
C0-15
AD0-1
CS
WR
NUMBER
A1, A9, A15, G1,
J15, Q1, Q7, Q15
A8, A14, B1, H1,
H15, P15, Q2, Q8
N8-11, P8-13,
Q9-14
N7, P7
P6
Q6
www.DataSheet4U.cCoLmK
Q5
ENPHREG
M1
ENOFREG
N1
ENCFREG
N5
ENPHAC
Q3
ENTIREG
P5
ENI Q4
MODPI/2PI
N6
CLROFR
P4
LOAD
MOD0-1
N4
M3, N3
PMSEL
RBYTILD
PACI
P3
L3
P2
TYPE
- +5V Power supply input.
DESCRIPTION
- Power supply ground input.
I Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.
I Address pins for selecting destination of C0-15 data.
I Chip Select (active low).
I Write Enable. Data is clocked into the register selected by AD0-1 on the rising edge of WR when
the CS line is low.
I Clock. All registers, except the control registers clocked with WR, are clocked (when enabled)
by the rising edge of CLK.
I Phase Register Enable (active low). Registered on chip by CLK. When active, after being
clocked onto chip, ENPHREG enables the clocking of data into the phase register.
I Frequency Offset Register Enable (active Low). Registered on chip by CLK. When active, after
being clocked onto chip, ENOFREG enables clocking of data into the frequency offset register.
I Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENCFREG enables clocking of data into the center frequency register.
I Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENPHAC enables clocking of the phase accumulator register.
I Time Interval Control Register Enable (active low). Registered on chip by CLK. When active,
after being clocked onto chip, ENTIREG enables clocking of data into the time accumulator
register.
I Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by
CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.
I Modulo π/2π Select. When low, the Sine and Cosine ROMs are addressed modulo 2π (360
degrees). When high, the most significant address bit is held low so that the ROMs are
addressed modulo π (180 degrees). This input is registered on chip by clock.
I Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,
after being clocked onto chip, CLROFR zeros the data path from the frequency offset register to
the frequency adder. New data can still be clocked into the frequency offset register; CLROFR
does not affect the contents of the register.
I Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback
path in the phase accumulator without clearing the phase accumulator register.
I External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90,
180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of
the phase control path are set to zero.
These bits are loaded into the phase register when ENPHREG is low.
I Phase Modulation Select Line. This line determines the source of the data clocked into the phase
register. When high, the phase control register is selected. When low, the external modulation pins
(MOD0-1) are selected for the most significant two bits and the least significant two bits and the
least significant 14 bits are set to zero. This control is registered by CLK.
I ROM Bypass, Timer Load. Active low, registered by CLK. This input bypasses the sine/ cosine
ROM so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go
directly to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the timer
accumulator register by zeroing the feedback in the accumulator.
I Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to
increment by one, in addition to the values in the phase accumulator register and frequency
adder.
5
5 Page 
HSP45116
PFCS appears on IOUT0-15 and the least significant bits
come out on ROUT0-15.
Complex Multiplier/Accumulator
The CMAC (Figure 2) performs two types of functions:
complex multiplication/accumulation for modulation and
demodulation of digital signals, and the operations
necessary to implement an FFT butterfly. Modulation and
demodulation are implemented using the complex multiplier
and its associated accumulator; the rest of the circuitry
in this section, i.e., the complex accumulator, input shifters
and growth detect logic are used along with the complex
multiplier/accumulator for FFTs. The complex multiplier
performs the complex vector multiplication on the output of
www.DataShetheet4US.icnoem/Cosine Section and the vector represented by the
real and imaginary inputs RIN and IIN. The two vectors are
combined in the following manner:
ROUT = COS x RIN - SIN x IIN
IOUT = COS x IIN + SIN x RIN
RIN and IIN are latched into the input registers and passed
through the shift stages. Clocking of the input registers is
enabled with a low on ENI. The amount of shift on the
latched data is programmed with SH0-1 (Table 3). The
output of the shifters is sent to the CMAC and the auxiliary
accumulators.
TABLE 3. INPUT SHIFT SELECTION
SH1 SH0
SELECTED BITS
0 0 RIN0-15, IMIN0-15
0 1 RIN1-16, IMIN1-16
1 0 RIN2-17, IMIN2-17
1 1 RIN3-18, IMIN3-18
The 33-bit real and imaginary outputs of the Complex
Multiplier are latched in the Multiplier Registers and then go
through the Accumulator Section of the CMAC. If the ACC
line is high, the feedback to the accumulators is enabled; a
low on ACC zeroes the feedback path, so that the next set of
real and imaginary data out of the complex multiplier is
stored in the CMAC Output Registers.
The data in the CMAC Output Registers goes to the
Multiplexer, the output of which is determined by the
OUTMUX0-1 lines (Table 4). BINFMT controls whether the
output of the Multiplexer is presented in two’s complement or
unsigned format; BINFMT = 0 inverts ROUT19 and IOUT19
for unsigned output, while BINFMT = 1 selects two’s
complement.
TABLE 4. OUTPUT MULTIPLEXER SELECTION
OUT OUT
MUX MUX
10
RO16-19
RO0-15
IO16-19
IO0-15
0 0 Real CMAC Real CMAC Imag CMAC Imag CMAC
31-34
15-30
31-34
15-30
0 1 Real CMAC 0, Real
Imag CMAC 0, Imag
31-34
CMAC 0-14 31-34
CMAC 0-14
1 0 Real ACC Real ACC Imag ACC Imag ACC
16-19
0-15
16-19
0-15
1 1 Reserved Reserved Reserved Reserved
The Complex Accumulator duplicates the accumulator in the
CMAC. The input comes from the data shifters, and its 20-bit
complex output goes to the Multiplexer. ACC controls
whether the accumulator is enabled or not. OUTMUX0-1
determines whether the accumulator output appears on
ROUT and IOUT.
11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 45116.PDF ] | |
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