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PDF HDJD-J822 Data sheet ( Hoja de datos )
| Número de pieza | HDJD-J822 | |
| Descripción | Agilent HDJD-J822-SCR00 Color Management System Feedback Controller | |
| Fabricantes | Agilent | |
| Logotipo |  |
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Agilent HDJD-J822-SCR00
Color Management System
Feedback Controller
Data Sheet
www.DataSheet4U.com
Description
The HDJD-J822 is a CMOS mixed-
signal IC designed to be the
optical feedback controller of an
LED-based lighting system. A
typical system consists of an
array of red, green and blue
LEDs, LED drivers, a tri-color
photosensor that samples the
light output, and the HDJD-J822.
The IC interfaces directly to the
photosensor, processes the color
information and adjusts the light
output from the LEDs until the
desired color is achieved. To
achieve this, the IC integrates a
high-accuracy 10-bit analog-to-
digital converter front-end, a
color data processing logic core,
and a high-resolution 12-bit PWM
output generator.
By employing a feedback system
and the HDJD-J822, the light
output produced by the LED
array maintains its color over
time and temperature. In
addition, the desired color can be
specified using a standard CIE
color space.
In addition, by incorporating a
standard I2C serial interface,
specifying the color of the LED
array’s light output is as simple as
picking the color coordinates
from the CIE color space and
writing several bytes of data to
the device.
The output PWM signals are
connected directly to the LED
drivers as enable signals. The
PWM signals control the on-time
duration of the red, green and
blue LEDs. That duration is
continually adjusted in real-time
to match the light output from the
LED array to the specified,
desired color.
Features
• –40 to 85°C operation
• I2C serial interface
• Robust CMOS-Schmitt input
• CMOS/TTL compatible output
• Multiple color input formats –
CIE XYZ, Yxy, Yu’v’ and RGB
• 3-channel analog interface to
color sensor – X, Y and Z channels
• 3-channel 12-bit PWM output –
Red, Green, and Blue LED channels
• Internal computation of calibration
data
• Internal clock generator
• Internal reference voltage
generator
• Error flag output
• External push-button interface
• Only passive components required
externally
Applications
• Backlighting
• General illumination
• Mood/accent lighting
• Color context sensitive appliances
1 page  
General Specifications
Feature
Interface
Input Color Format
Input Sensor Signal
Minimum Dynamic Range
Output PWM Frequency
Output PWM Resolution
Error Flag
Device Address Control
www.DataSheet4U.com
Supply
I/O
Value
I2C 100 kHz
CIE XYZ, Yxy, Yu’v’ and RGB (illuminant E)
0 to 2.5 V (typical configuration)
Sensor output > 500 (ADC output code, each channel)
during calibration
610 Hz nominal (typical configuration)
12 bits
Assertion on ERR_FLAG pin indicates an error condition
Upper 5 bits 10101 binary, lower 2 bits defined by
A1:A0 pins in that order
5 V digital, 5 V analog (nominal)
Schmitt-CMOS input and CMOS/TTL compatible output
Block Diagram
VREF_EXT
CLK_EXT
ROSC
XRST
SENSE_X
SENSE_Y
SENSE_Z
TEST
SLEEP
CLK_SEL
SDA
SCL
A1
A0
DVDD
DVSS
AVDD
AVSS
VREF
REFERENCE
VOLTAGE
CLOCK MUX
PROGRAMMABLE
AMPLIFIER
ADC SENSOR
INTERNAL
OSCILLATOR
PUSH_BUTTON
DUTY FACTOR
MODE SELECT
I2C
INTERFACE
CONTROL
INTERNAL REGISTERS
CONTROL
CONFIG
DATA:
SETPOINT
CALIBRATION
SYSTEM CONTROLLER
COLOR
CONTROLLER
CONTROL
SIGNALS
BRIGHT
COLOR
PWM_R
PWM_G
PWM_B
ERR_FLAG
5
5 Page 
Notes on Sampling Frequency and
PWM Output Frequency
The sampling frequency, fSAMP,
which is the frequency at which
HDJD-J822 samples the tricolor
photosensor, is related to the
system clock frequency, fCLK.
The output PWM frequency,
fPWM, is also related to fCLK. The
system clock is sourced from
either the internal oscillator or
an external clock.
www.DataSheet4UC.caolmculation example:
fCLK = 2.5 MHz (nominal)
fSAMP = fCLK/25087 = 100 Hz
(nominal)
fPWM = fCLK/4095 = 610 Hz
(nominal)
The internal oscillator frequency
varies from part-to-part but it
will not vary significantly during
operation.
Register Description
The user controls and configures
HDJD-J822 by programming a
set of internal registers, through
the I2C protocol. Refer to
Application Note 5070 for
programming guide and register
description.
I2C Interface
Description
The programming interface to
HDJD-J822 is a standard 2-wire
serial bus, which follows the I2C
data transmission protocol. This
protocol defines a transmitter
as a device that sends data to
the bus and a receiver as a
device that receives data from
the bus.
A master is a device that
initiates a data transfer on the
bus, generates the clock signal
and terminates the data
transfer. A device addressed by
the master is called a slave. Both
master and slave can act as a
transmitter or a receiver but the
master controls the direction for
data transfer.
The bus consists of a serial clock
(SCL) and a serial data (SDA)
line. Both lines are bi-directional
and connected to the positive
power supply through a pull-up
resistor. When the bus is free,
both lines are HIGH.
HDJD-J822’s I2C bus interface
always operates as a slave
transceiver in standard mode.
Standard mode has a data
transfer rate of up to 100 kbit/s.
START/STOP Condition
To begin an I2C data transfer,
the master must send a unique
signal to the bus called a START
condition. This is defined as a
HIGH to LOW transition on the
SDA line while SCL is HIGH.
The master terminates the
transfer by sending another
unique signal to the bus called a
STOP condition. This is defined
as a LOW to HIGH transition on
the SDA line while SCL is HIGH.
The bus is considered to be busy
after a START (S) condition. It
will be considered free a certain
time after the STOP (P)
condition. The bus stays busy if
a repeated START (Sr) is sent
instead of a STOP condition.
The START and repeated START
conditions are functionally
identical.
SDA
SCL S
START CONDITION
Figure 2. START/STOP condition.
P
STOP CONDITION
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet HDJD-J822.PDF ] | |
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