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PDF NCP5393 Data sheet ( Hoja de datos )
| Número de pieza | NCP5393 | |
| Descripción | 2/3/4-Phase Controller | |
| Fabricantes | ON Semiconductor | |
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NCP5393
2/3/4-Phase Controller for
CPU Applications
The NCP5393 controls up to four VDD phases and one VDDNB
phase to provide a buck regulator solution for current and
next-generation AMD processors. The NCP5393 incorporates
differential voltage sensing, differential phase current sensing,
optional load-line voltage positioning, and programmable VDD and
VDDNB offsets to provide accurately regulated power parallel- and
serial-VID AMD processors. Dual-edge multiphase modulation
provides the fastest initial response to dynamic load events. This
reduces system cost by requiring less bulk and ceramic output
capacitance to meet transient regulation specifications.
High performance operational error amplifiers are provided to
simplify compensation of the VDD and VDDNB regulators. Dynamic
Reference Injection further simplifies loop compensation by
www.DataSheelimeti4nUati.ncgomthe need to compromise between response to load
transients and response to VID code changes.
Features
•ăMeets AMD's Parallel, Serial (SVI) and Hybrid VR Specifications
•ăUp to Four VDD Phases
•ăSingle-Phase VDDNB Controller
•ăDual-Edge PWM for Fastest Initial Response to Transient Loading
•ăHigh Performance Operational Error Amplifiers
•ăInternal Soft Start and Slew Rate Limiting
•ăDynamic Reference Injection (Patent #US07057381)
•ăDAC Range from 12.5 mV to 1.55 V
•ă$0.5% DAC Accuracy fro 0.8 V to 1.55 V
•ăVDD and VDD Offset Ranges 0 mV - 800 mV
•ăTrue Differential Remote Voltage Sense Amplifiers
•ăPhase-to-Phase IDD Current Balancing
•ăDifferential Current Sense Amplifiers for Each Phase of Each Output
•ă“Lossless” Inductor Current Sensing for VDD and VDDNB Outputs
•ăSupports Load Lines (Droop) for VDD and VDDNB Outputs
•ăOscillator Range of 100 kHz - 1 MHz
•ăTracking Over Voltage Protection
•ăOutput Inductor DCR-Based Over Current Protection for VDD and
VDDNB Outputs
•ăGuaranteed Startup into Precharged Loads
•ăTemperature Range: 0°C to 70°C
•ăThis is a Pb-Free Device*
Applications
•ăDesktop Processors
•ăServer Processors
•ăHigh-End Notebook PCs
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAM
1
1 48
QFN48, 7x7
CASE 485AJ
NCP5393
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NCP5393MNR2G QFN48 2500 / Tape & Reel
(Pb-Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©Ă Semiconductor Components Industries, LLC, 2008
February, 2008 - Rev. 0
1
Publication Order Number:
NCP5393/D
1 page  
NCP5393
NCP5393 PIN DESCRIPTIONS
Pin No.
Symbol
Description
1
VCCA
5 V supply pin for the NCP5393. The VCC bypassing capacitance must be connected between this
pin and GND (preferably returned to the package flag).
2
GND
Small-signal power supply return. This pin should be tied directly to the package flag (exposed pad).
3
COMP
Output of the voltage error amplifier for the VDD regulator.
4 FB Voltage error amplifier inverting input for the VDD regulator.
5
DROOP
Voltage output signal proportional to total current drawn from the VDD regulator. Used when load line
operation (“droop”) is desired.
6
VS+
Non-inverting input to the differential remote sense amplifier for the VDD regulator.
7 VS- Inverting input to the differential remote sense amplifier for the VDD regulator.
8
OFFSET
Input for offset voltage to be added to the VDD DAC's output voltage. Ground this pin for zero VDD
offset.
9 DIFFOUT
10 VFIX
www.DataSheet141U.com 12VMON
12 PSI_L
Output of the differential remote sense amplifier for the VDD regulator.
When pulled low, this pin causes the levels on the SVC (VID3) and SVD (VID2) pins to be decoded
as a two-bit DAC code, which controls the VDD and VDDNB outputs.
UVLO monitor input for the 12 V power rail.
Power Saving Control. Low = single phase operation, High = normal operation. This pin is not used in
SVI mode.
13 CS1 Non-inverting input to current sense amplifier #1 for the VDD regulator. See Table: “Pin Connections
vs. Phase Count”
14
CS1N
Inverting input to current sense amplifier #1 for the VDD regulator. See Table: “Pin Connections vs.
Phase Count”
15 CS2 Non-inverting input to current sense amplifier #2 for the VDD regulator. See Table: “Pin Connections
vs. Phase Count”
16
CS2N
Inverting input to current sense amplifier #2 for the VDD regulator. See Table: “Pin Connections vs.
Phase Count”
17 CS3 Non-inverting input to current sense amplifier #3 for the VDD regulator. See Table: “Pin Connections
vs. Phase Count”
18
CS3N
Inverting input to current sense amplifier #3 for the VDD regulator. See Table: “Pin Connections vs.
Phase Count”
19 CS4 Non-inverting input to current sense amplifier #4 for the VDD regulator. See Table: “Pin Connections
vs. Phase Count”
20
CS4N
Inverting input to current sense amplifier #4 for the VDD regulator. See Table: “Pin Connections vs.
Phase Count”
21 ILIM Overcurrent shutdown threshold for VDD and VDDNB. A resistor divider from ROSC to GND is typic‐
ally used to develop an appropriate voltage on ILIM.
22
VCCB
5 V supply pin. Tie this pin to VCCA (Pin 1).
23
NB_CS
Non-inverting input to the current sense amplifier for the VDDNB regulator
24
NB_CSN
Inverting input to the current sense amplifier for the VDDNB regulator
25
VID4
Parallel Voltage ID DAC Input 4. Not used in SVI mode.
26
VID5
Parallel Voltage ID DAC Input 5. Not used in SVI mode.
27
ROSC
A resistance from this pin to ground programs the VDD and VDDNB oscillator frequencies. This pin
supplies a trimmed output voltage of 2 V.
28 NB_DIFFOUT Output of the differential remote sense amplifier for the VDDNB regulator.
29 NB_OFFSET Input for offset voltage to be added to the VDDNB DAC's output voltage. Ground this pin for zero
VDDNB offset.
30
NB_VS-
Inverting input to the differential remote sense amplifier for the VDDNB regulator.
31
NB_VS+
Non-inverting input to the differential remote sense amplifier for the VDDNB regulator.
http://onsemi.com
5
5 Page 
NCP5393
ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°CvTAv70°C; 4.75 VvVCCv5.25 V; All DAC Codes; CVCC = 0.1 mF)
Parameter
Test Conditions
Min Typ Max Unit
PSI_L (Power Saving Control, Active Low) (This pin is used in PVI mode only)
PSI_L Input Voltage (High)
PSI_L Input Voltage (Low)
PSI_L Hysteresis
CURRENT LIMIT
VHIGH
VLOW
VHIGH - VLOW or VLOW - VHIGH
0.9 - - V
- - 0.6 V
100 mV
Current Sense Amp to ILIM Gain
20 mV < (CSx - CSxN) < 60 mV (CS inputs tied)
5.7 6.0 6.3 V/V
ILIM Pin Input Bias Current
- - 0.5 mA
ILIM Pin Working Voltage Range
(NoteĂ3)
0.2 - 2.0 V
ILIM Offset Voltage
Offset extrapolated to CSx-CSxN = 0 V, and referred
-
30
- mV
to the ILIM pin
Delay
- 600 -
ns
VDDNB Current Limit Coefficient
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OFFSET INPUTS (VDD & VDDNB)
Output Offset Voltage Above VDAC
= N x VNBILIM /VILIM, where N = number of VDD
phases, and VNBILIM is the equivalent voltage
threshold for NB Current Limit resulting from VILIM.
1.0 V
0 - 800 mV
OUTPUT OVERVOLTAGE PROTECTION (VDD & VDDNB)
Over Voltage Threshold
In normal operation, with no VID changes
VDAC
+ 250
mV
VCCA UNDERVOLTAGE PROTECTION
VCCA UVLO Start Threshold
4.0 4.25 4.5
V
VCCA UVLO Stop Threshold
3.8 4.05 4.3
V
VCCA UVLO Hysteresis
200 mV
INPUT SUPPLY CURRENT
VCC Operating Current
ENABLE held Low, No PWM operation
- 25 35 mA
12VMON
12VMON (High Threshold)
8 8.5 9
V
12VMON (Low Threshold)
7 7.5 8
V
12VMON Hysteresis
Low - High or High - Low
1.0 V
3. Guaranteed by design. Not production tested.
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet NCP5393.PDF ] | |
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