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PDF S5933QE Data sheet ( Hoja de datos )
| Número de pieza | S5933QE | |
| Descripción | PCI Interface Device Summary | |
| Fabricantes | AMCC | |
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PCI Interface Device Summary
S5933QE
Revision 4 January 6, 1999
Factory Device Update
The following are all known device and document errors for the AMCC S5933 PCI Matchmaker revision QE and
the 1998 device data book. The workarounds described below are factory suggestions and are not to imply the only
or all possible solutions. Contact your local Field Application Engineer for new workaround developements. Also
contact your AMCC FAE or local Insight Technical Sales Engineer for the latest design notes and data book
corrections or see the AMCC home page at www.amcc.com.
D8: Bus Master Burst Write Operation with an Asynchronous FIFO Interface
Description: When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933
deasserts FRAME# on the next clock to indicate the last data phase is in progress. If another value is written from the
add-on at the right moment, an internal condition may cause IRDY# to remain asserted to sustain the burst, but FRAME#
has already been deasserted.
Workaround: Externally synchronizing WRFIFO# or WR# to BPCLK moves the rising edge of the write strobe to prevent this
event from occurring. Request separate D8 applications note from your local FAE or Insight TSE for more detail.
Status: No factory plan to re-spin.
D14.1: False Add-On to PCI FIFO Empty Indication
Description: If the last data in the Add-On to PCI FIFO is written by the S5933 to the PCI bus and receives a target retry, the
FWE output and Add-On to PCI FIFO status bits will go active, indicating that the FIFO is empty, even though the final
data has not yet been transferred. This is only a problem when using Add-On initiated bus mastering when FWE is used
as a condition to deassert AMWEN at the end of a bus master write. Using FWE in this way could cause AMWEN to be
deasserted before the last bus master write has successfully completed.
Workaround: Instead of using FWE, the Add-On interrupt signal, IRQ#, can be configured to go active when the transfer count
reaches zero. The transfer count is only updated when data is successfully written. Request separate D14.1 applications
note from your local FAE or Insight TSE for more detail.
NOTE: When FWE and the status bits indicate that the Add-On to PCI FIFO is empty, there are 8 empty locations in the FIFO.
The data for the transfer which received the retry is stored in a holding register and is not involved.
Status: No factory plan to re-spin.
D17: PCI to Add-On FIFO Loses Data when Written w/o all PCI Byte Enables Asserted
Description: When writing to the FIFO from the PCI side (as a target), if the byte enable for the specified byte lane is not
active, then that data could be lost. The problem is encountered when the S5933 Operation Registers are mapped to I/O
space and the FIFO is written to 16 bits at a time, alternating between bytes 0,1 and bytes 2,3. Under certain conditions
internal to the S5933, when the byte enable for the FIFO advance byte lane is not active, the data written is not captured
by the FIFO.
Workaround 1: Always write the FIFO with the byte enable that corresponds to the FIFO advance byte lane active.
Workaround 2: Always perform 32-bit FIFO writes from the PCI bus.
Status: No factory plan to re-spin.
6290 Sequence Drive, San Diego, California 92121-4358
800-755-2622 Fax: 619-450-9885
http://www.amcc.com
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5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet S5933QE.PDF ] | |
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