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PDF DS1685 Data sheet ( Hoja de datos )
| Número de pieza | DS1685 | |
| Descripción | (DS1685 / DS1687) 3V/5V Real-Time Clocks | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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www.maxim-ic.com
FEATURES
Incorporates Industry-Standard DS1287 PC Clock
plus Enhanced Features Such as:
§ Y2K Compliant
§ +3V or +5V Operation
§ 64-Bit Silicon Serial Number
§ Power-Control Circuitry Supports System Power-
On from Date/Time Alarm or Key Closure
§ 32kHz Output for Power Management
§ Crystal-Select Bit Allows RTC to Operate with
6pF or 12.5pF Crystal
§ SMI Recovery Stack
§ 242 Bytes Battery-Backed NV RAM
§ Auxiliary Battery Input
DS1685/DS1687
3V/5V Real-Time Clocks
§ RAM Clear Input
§ Century Register
§ Date Alarm Register
§ Compatible with Existing BIOS for Original
DS1287 Functions
§ Available as Chip (DS1685) or Stand-Alone
Encapsulated DIP (EDIP) with Embedded
Battery and Crystal (DS1687)
§ Timekeeping Algorithm Includes Leap-Year
Compensation Valid Through 2099
§ Underwriters Laboratory (UL) Recognized
APPLICATIONS
Embedded Systems
Utility Meters
Security Systems
Network Hubs, Bridges, and Routers
PIN CONFIGURATIONS
TOP VIEW
PWR
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1 24
2 DS1685/ 23
3 DS1685S/ 22
4 DS1685E 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
SQW
VBAUX
RCLR
VBAT
IRQ
KS
RD
GND
WR
ALE
CS
DIP (0.600”)/
SO (0.300”)/
TSSOP (0.173”)
PACKAGE DIMENSION
INFORMATION
www.maxim-ic.com/DallasPackInfo
AD0
AD1
AD2
AD3
AD4
AD5
N.C.
4 3 2 1 28 27 26
5 25
6
7
DS1685Q
24
23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
RCLR
VBAT
IRQ
KS
RD
GND
WR
PLCC
PWR
N.C.
N.C.
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1
2 DS1687
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
EDIP (740 mil)
VCC
SQW
VBAUX
RCLR
N.C.
IRQ
KS
RD
N.C.
WR
ALE
CS
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 032604
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DS1685/DS1687 3V/5V Real-Time Clocks
PIN DESCRIPTIONS (continued)
PIN
DS1685
DIP, SO,
TSSOP
PLCC
18 22
19 23
20 24
21 25
22 26
23 27
24 28
DS1687
EDIP
18
19
—
21
22
23
24
NAME
FUNCTION
KS
IRQ
VBAT
RCLR
VBAUX
SQW
VCC
Kickstart Input, Active Low. When VCC is removed from the
DS1685/DS1687, the system can be powered on in response to an active-
low transition on the KS pin, as might be generated from a key closure.
VBAUX must be present and the auxiliary-battery enable bit (ABE) and kick-
start enable bit (KSE) must be set to 1 if the kickstart function is used, and
the KS pin must be pulled up to the VBAUX supply. While VCC is applied, the
KS pin can be used as an interrupt input. If not used, connect to VCC, or to
VBAUX if VBAUX is used.
Interrupt-Request Output, Open Drain, Active Low. The IRQ pin is an
active-low output of the DS1685/DS1687 that can be connected to the
interrupt input of a processor. The IRQ output remains low as long as the
status bit causing the interrupt is present and the corresponding interrupt-
enable bit is set. To clear the IRQ pin, the application software must clear
all the enabled flag bits contributing to IRQ’s active state asserted but
without asserting CS latch addresses. However, no data transfer occurs.
Battery input for any standard 3V lithium cell or other energy source.
Battery voltage must be held between 2.5V and 3.7V for proper operation.
VBAT must be grounded if not used. Diodes should not be placed between
VBAT and the battery. See “Conditions of Acceptability” at
www.maxim-ic.com/UL.
RAM Clear Input, Active Low. If enabled by software, taking RCLR low
clears the 242 bytes of user RAM to FFh. When enabled, RCLR can be
activated whether or not VCC is present. The RCLR function is designed to
be used by a human interface (shorting to ground manually or by a switch)
and not to be driven with external buffers. This pin is internally pulled up.
Do not use an external pullup resistor on this pin.
Auxiliary Battery Input. Required for kickstart and wake-up features. This
input also supports clock/ calendar and user RAM if VBAT is at lower voltage
or is not present. A standard +3V lithium cell or other energy source can be
used. Battery voltage must be held between +2.5V and +3.7V for proper
operation. If VBAUX is not going to be used it should be grounded, and
Auxiliary-Battery Enable bit bank 1, register 4BH, should be written to 0.
See “Conditions of Acceptability” at www.maxim-ic.com/UL.
Square-Wave Output. The SQW pin provides a 32kHz square-wave output,
tREC, after a power-up condition has been detected. This condition sets the
following bits, enabling the 32kHz output; DV1 = 1, and E32K = 1. A square
wave is output on this pin if either SQWE = 1 or E32K = 1. If E32K = 1, then
32kHz is output regardless of the other control bits. If E32K = 0, then the
output frequency is dependent on the control bits in register A. The SQW
pin can output a signal from one of 13 taps provided by the 15 internal
divider stages of the RTC. The frequency of the SQW pin can be changed
by programming Register A as shown in Table 3. The SQW signal can be
turned on and off using the SQWE bit in register B or the E32K bit in
extended register 4Bh. A 32kHz SQW signal is output when the enable-
32kHz (E32K) bit in extended register 4Bh is a logic 1 and VCC is above
VPF. A 32kHz square wave is also available when VCC is less than VPF if
E32K = 1, ABE = 1, and voltage is applied to the VBAUX pin.
DC Power for Primary Power Supply. When VCC is applied within the
normal limits, the device sis fully accessible and data can be written and
read. When VCC is below VPF reads and writes are inhibited.
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DS1685/DS1687 3V/5V Real-Time Clocks
CONTROL REGISTERS
The four control registers A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible at all
times, even during the update cycle.
Register A (0Ah)
MSB
BIT 7
BIT 6
UIP DV2
BIT 5
DV1
BIT 4
DV0
BIT 3
RS3
BIT 2
RS2
BIT 1
RS1
LSB
BIT 0
RS0
UIP – The update-in-progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the update
transfer occurs soon. When UIP is a 0, the update transfer does not occur for at least 244ms. The time, calendar,
and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read-only. Writing
the SET bit in Register B to a 1 inhibits any update transfer and clears the UIP status bit.
DV2, DV1, DV0 - These three bits are used to turn the oscillator on or off and to reset the countdown chain. A
pattern of 01X is the only combination of bits that will turn the oscillator on and allow the RTC to keep time. A
pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update will occur at
500ms after a pattern of 01X is written to DV0, DV1, and DV2. The oscillator enable bit, DV1, will be set to a 1
when VCC is applied.
DV2 = Countdown Chain
1 – resets countdown chain only if DV1=1
0 – countdown chain enabled
DV1 = Oscillator Enable
1 – oscillator on
0 – oscillator off
DV0 = Bank Select
1 – extended registers
0 – original bank
RS3, RS2, RS1, RS0 – These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable
the divider output. The tap selected can be used to generate an output square wave (SQW pin) and/or a periodic
interrupt. The user can do one of the following:
1) Enable the interrupt with the PIE bit;
2) Enable the SQW output pin with the SQWE or E32K bits;
3) Enable both at the same time and the same rate; or
4) Enable neither.
Table 3 lists the periodic interrupt rates and the square-wave frequencies that can be chosen with the RS bits.
11 of 33
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| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet DS1685.PDF ] | |
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