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PDF DM9131 Data sheet ( Hoja de datos )
| Número de pieza | DM9131 | |
| Descripción | 10/100Mbps Fast Ethernet Physical Layer Single Chip Transceiver | |
| Fabricantes | Davicom Semiconductor Incorporated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DM9131 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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DM9131
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
General Description
The DM9131 is a physical-layer, single-chip, low-
power transceiver for 100BASE-TX and 10BASE-T
operations. On the media side, it provides a direct
interface either to Unshielded Twisted Pair Cable 5
(UTP5) for 100BASE-TX Fast Ethernet, or
UTP5/UTP3 Cable for 10BASE-T Ethernet, and it also
provides PECL interface to connect the external fiber
optical transceiver. Through the Media Independent
Interface (MII), the DM9131 connects to the Medium
Access Control (MAC) layer, ensuring a high inter-
operability among products from different vendors.
The DM9131 uses a low-power and high-performance
CMOS process. It contains the entire physical layer
functions of 100BASE-TX as defined by IEEE802.3u,
including the Physical Coding Sublayer (PCS),
Physical Medium Attachment (PMA), Twisted Pair
Physical Medium Dependent Sublayer (TP-PMD),
10BASE-TX Encoder/Decoder (ENC/DEC), and
Twisted Pair Media Access Unit (TPMAU). The
DM9131 provides a strong support for the auto-
negotiation function utilizing automatic media speed
and protocol selection. Furthermore, due to the built-
in wave-shaping filter, the DM9131 needs no external
filter to transport signals to the media in 100M or 10M
Ethernet operation.
Block Diagram
100Base-FX
PECL
Interface
100Base-TX
Transceiver
Clock
Circuit
Block
100Base-
TX
PCS
MII
Interface
10Base-T
TX/RX Module
Auto-Negotiation
Biasing/
Power
Block
MII
Register
LED Driver
MII
Management
Control
Final
Version: DM9131-DS-F01
April 7, 2000
1
1 page  
www.DataSheet4U.com
Pin Configuration
DM9131
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
NC
BGRESG
BGRES
NC
AVCC
AVCC
RX+/FXRD+
RX-/FXRD-
AGND
AGND
AGND
AGND
TX+/FXTD+
TX-/FXTD-
NC
AVCC
PLLVCC
NC
PLLGND
DGND
NC
OPMODE0
OPMODE1
OPMODE2
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DM9131
75 NC
74 NC
73 RESET#
72 NC
71 DVCC
70 NC
69 RXEN
68 RXER/RXD[4]/RPTR
67 RXDV
66 COL
65 CRS/BP4B5B
64 RXCLK
63 MDINTR#
62 NC
61 RXD[0]
60 RXD[1]
59 RXD[2]
58 RXD[3]
57 NC
56 DVCC
55 NC
54 MDIO
53 MDC
52 NC
51 NC
Final
Version: DM9131-DS-F01
April 7, 2000
5
5 Page 
www.DataSheet4U.com
DM9131
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
MII Register Description
ADD
00
01
02
03
04
05
06
16
17
18
21
22
23
Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
CONTROL Reset Loop Speed Auto-N Power Isolate Restart Full Coll.
Reserved
back select Enable Down
Auto-N Duplex Test
STATUS T4 TX FDX TX HDX 10 FDX 10 HDX
Reserved
Pream. Auto-N Remote Auto-N Link Jabber Extd
Cap. Cap. Cap. Cap. Cap.
Supr. Compl. Fault Cap. Status Detect Cap.
PHYID1
0
0
000 0 0
1
100 0
0
00
0
PHYID2
1
0
111 0
Model No.
Version No.
Auto-Neg. Next FLPRcv Remote Reserved
FC T4 TX FDX TX HDX 10 FDX 10 HDX
Advertised Protocol Selector Field
Advertise Page Ack Fault
Adv Adv Adv Adv Adv Adv
Link Part. LPNext LP LP Reserved LP LP LP LP LP LP
Link Partner Protocol Selector Field
Ability Page Ack RF
FC T4 TX FDX TX HDX 10 FDX 10 HDX
Auto-Neg.
Reserved
Pardet LPNext Next Pg New Pg LPAutoN
Expansion
Fault Pg Able Able Rcv Cap.
Aux.
BP BP BP BP_AD Repeat TX/FX FEF RMII Force SPDLE Rsvd FDXLE Reset Pream. Sleep Remote
Config. 4B5B SCR ALIGN POK mode Select Enable Enable 100LNK D_CTL
D_CTL St. Mch Supr. mode LoopOut
Aux.
100 100
10 10 HDX
Reserved
PHY ADDR [4:0]
Auto-N. Monitor Bit [3:0]
Conf/Stat FDX HDX FDX
10T Rsvd LP HBE SQUE JAB 10T
Reserved
Polarity
Conf/Stat
Enable Enable Enable Enable Serial
Reverse
MDINTR INTR Rsvd Rsvd Rsvd FDX SPD Link INTR Rsvd Rsvd Rsvd FDX SPD Link INT INTR
PEND
Mask Mask Mask Mask
Change Change Change Enable Status
Rcv Error
Receive Error Counter
Counter
Disconnect
Reserved
Disconnect Counter
Counter
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
'Where
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
(PIN#) Value latched in from pin # at reset
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
Final
Version: DM9131-DS-F01
April 7, 2000
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM9131.PDF ] | |
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