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PDF LV5609LP Data sheet ( Hoja de datos )

Número de pieza LV5609LP
Descripción Bi-CMOS LSI
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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No Preview Available ! LV5609LP Hoja de datos, Descripción, Manual

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Ordering number : ENA0692
LV5609LP
Bi-CMOS LSI
For CCD
Vertical Clock Driver
Overview
The LV5609LP is vertical clock driver for CCD.
Functions
Ternary output ×2ch
Binary output ×2ch
SHT output ×1ch
Output ON resistance : 30Ω typ
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = VM = 0V
Parameter
Symbol
Conditions
Maximum supply voltage
VDD max
VH max
VL max
VH-VL max
Allowable power dissipation
Pd max
with specified substrate *
Operating temperature
Topr
Storage temperature
Tstg
* : Specified substrate : 40×50×0.8mm3, glass epoxy four-layer (2S2P) board
Allowable Operating Ratings at Ta = 25°C, VSS = VM = 0V
Parameter
Symbol
Conditions
Supply voltage
CMOS input High voltage
CMOS input Low voltage
VDD
VH
VL
VH-VL
VINH
VINL
Ratings
6
20
-10
24
0.8
-20 to +80
-40 to +125
Unit
V
V
V
V
W
°C
°C
min
2.0
-8.5
Ratings
typ
3.3
15
-7.5
0.8VDD
-0.1
max
5.5
17
-4
23.5
VDD
0.4
Unit
V
V
V
V
V
V
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
32207 MS PC 20060719-S00002 No.A0692-1/8

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LV5609LP pdf
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Block Diagram
VDD 20
0.1μF
XV1 12
XSG1 13
XV2 14
Input Buffer
XV3 15
XSG3 16
XV4 17
XSHT 18
VSS
21
LV5609LP
Level Shift
& Output Buffer
30
30
30
30
30
9 VH
6 V1
1μF
5 V2
VM
7
4 V3
3 V4
2 SHT
VL
1
1μF
Logical Function Table
Input
XV1 XSG1 XV2
XSHT
XV3 XSG3 XV4
L LXX
Output
V1 V2
SHT
V3 V4
VH X
X
L H X X VM X X
H L X X VL X X
H H X X VL X X
X X L X X VM X
X X H X X VL X
X X X L X X VH
X X X H X X VL
No.A0692-5/8

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