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PDF S25FL128P Data sheet ( Hoja de datos )
| Número de pieza | S25FL128P | |
| Descripción | 128 Megabit CMOS 3.0 Volt Flash Memory | |
| Fabricantes | SPANSION | |
| Logotipo |  |
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S25FL128P
128 Megabit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Bus
Data Sheet
S25FL128P Cover Sheet
This product is not recommended for new and current designs. For new and current designs,
S25FL128S supersedes S25FL128P. This is the factory-recommended migration path. Please refer to
the S25FL128S data sheet for specifications and ordering information.
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S25FL128P_00
Revision 12
Issue Date Janauary 29, 2013
1 page  
Data Sheet
Figures
Figure 2.1 16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.2 8-Pin WSON Package (6 x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6.1 Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6.2 SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7.1 Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11.1 Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11.2 Parallel Read Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.3 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 21
Figure 11.4 Read Identification Command Sequence and Data Out Sequence. . . . . . . . . . . . . . . . . . . . 22
Figure 11.5 Parallel Read_ID Command Sequence and Data Out Sequence . . . . . . . . . . . . . . . . . . . . . 23
Figure 11.6 Serial READ_ID Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11.7 Parallel Read_ID Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11.8 Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11.9 Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11.10 Read Status Register (RDSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11.11 Parallel Read Status Register (RDSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 11.12 Write Status Register (WRSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11.13 Parallel Write Status Register (WRSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11.14 Page Program (PP) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11.15 Parallel Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11.16 Sector Erase (SE) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11.17 Bulk Erase (BE) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11.18 Deep Power Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11.19 Release from Deep Power Down (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11.20 Serial Release from Deep Power Down and
Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 11.21 Parallel Release from Deep Power Down and
Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 12.1 ACC Program Acceleration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 13.1 Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13.2 Power-down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 15.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 15.2 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 19.1 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 19.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . 45
Janauary 29, 2013 S25FL128P_00_12
S25FL128P
5
5 Page 
Data Sheet
6. Spansion SPI Modes
A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices:
CPOL = 0, CPHA = 0 (Mode 0)
CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for
both modes.
When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes:
SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)
SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)
Figure 6.1 Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
Bus Master
SO
SI
SCK
SCK SO SI
SCK SO SI
SCK SO SI
CS3 CS2 CS1
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS#
HOLD# CS#
HOLD#
WP#/ACC
WP#/ACC
CS# HOLD#
WP#/ACC
Note
The Write Protect/Accelerated Programming (WP#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0)
as appropriate.
Figure 6.2 SPI Modes Supported
CS#
CPOL CPHA
Mode 0 0
0 SCK
Mode 3 1
1 SCK
SI
MSB
SO MSB
Janauary 29, 2013 S25FL128P_00_12
S25FL128P
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S25FL128P.PDF ] | |
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