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Nanya Technology - (NT5SVxxMxxBx) 256Mb SDRAM

Numéro de référence NT5SV64M4BS
Description (NT5SVxxMxxBx) 256Mb SDRAM
Fabricant Nanya Technology 
Logo Nanya Technology 





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NT5SV64M4BS fiche technique
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NT5SV64M4BS / NT5SV64M4BT
NT5SV32M8BS / NT5SV32M8BT
NT5SV16M16BS / NT5SV16M16BT
256Mb Synchronous DRAM
Features
High Performance:
fCK Clock Frequency
tCK Clock Cycle
tAC Clock Access Time1
tAC Clock Access Time2
6K
CL=3
75B
CL=3
Units
166 133 MHz
6 7.5 ns
— — ns
5 5.4 ns
1. Terminated load. See AC Characteristics on page 37
2. Unterminated load. See AC Characteristics on page
37
3. tRP = tRCD = 2 CKs
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BA0/BA1 (Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8
• Programmable Wrap: Sequential or Interleave
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard Power operation
• 8192 refresh cycles/64ms
• Random Column Address every CK (1-N Rule)
• Single 3.3V ± 0.3V Power Supply
• LVTTL compatible
• Package: 54-pin 400 mil TSOP-Type II
• Lead-free & Halogen-free product available
Description
The NT5SV64M4BS, NT5SV64M4BT, NT5SV32M8BS,
NT5SV32M8BT, NT5SV16M16BS, and NT5SV16M16BT are
four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O
x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4
Bank, respectively. These synchronous devices achieve
high-speed data transfer rates of up to 166MHz by employing
a pipeline chip architecture that synchronizes the output data
to a system clock.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fifteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Thirteen row addresses (A0-A12) and two
bank select addresses (BA0, BA1) are strobed with RAS.
Eleven column addresses (A0-A9, A11) plus bank select
addresses and A10 are strobed with CAS. Column address
A11 is dropped on the x8 device, and column addresses A11
and A9 are dropped on the x16 device.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A12, BA0, BA1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache
operation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 166MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are sup-
ported.
REV 1.4
Oct 2006
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.

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