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PDF P14NK50Z Data sheet ( Hoja de datos )

Número de pieza P14NK50Z
Descripción STP14NK50Z
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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STP14NK50Z - STP14NK50ZFP
STB14NK50Z-STB14NK50Z-1-STW14NK50Z
N-channel 500V - 0.34- 14A TO-220/FP/D2PAK/I2PAK/TO-247
Zener-protected SuperMESHTM Power MOSFET
General features
Type
STP14NK50Z
STP14NK50ZFP
STB14NK50Z
STB14NK50Z-1
STW14NK50Z
VDSS
500V
500V
500V
500V
500V
RDS(on)
<0.38
<0.38
<0.38
<0.38
<0.38
ID
14A
14A
14A
14A
14A
Pw
150W
35W
150W
150W
150W
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitances
Very good manufacturing repeatibility
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs including revolutionary
MDmesh™ products.
Applications
Switching application
3
2
1
TO-220
TO-247
123
I2PAK
3
2
1
TO-220FP
3
1
D2PAK
Internal schematic diagram
Order codes
Part number
STP14NK50Z
STP14NK50ZFP
STB14NK50ZT4
STB14NK50Z-1
STW14NK50Z
July 2006
Marking
P14NK50Z
P14NK50ZFP
B14NK50Z
B14NK50Z
W14NK50Z
Package
TO-220
TO-220FP
D2PAK
I2PAK
TO-247
Rev 3
Packaging
Tube
Tube
Tape & reel
Tube
Tube
1/19
www.st.com
19

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P14NK50Z pdf
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STP14NK50Z - STP14NK50ZFP - STB14NK50Z - STB14NK50Z-1 - STW14NK50Z Electrical charac-
2 Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
IDSS
Zero gate voltage drain
current (VGS = 0)
IGSS
VGS(th)
RDS(on)
Gate body leakage current
(VDS = 0)
Gate threshold voltage
Static drain-source on
resistance
ID = 1mA, VGS= 0
VDS = Max rating,
VDS = Max rating, TC
=125°C
VGS = ±20V
VDS= VGS, ID = 100µA
VGS= 10V, ID= 6A
Min. Typ. Max. Unit
500 V
1 µA
50 µA
±10 nA
3 3.75 4.5 V
0.34 0.38
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1) Forward transconductance VDS =8V, ID = 6A
12 S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25V, f=1 MHz, VGS=0
2000
238
55
pF
pF
pF
Coss
(2)
eq .
Equivalent output
capacitance
VGS=0, VDS =0V to 400V
150 pF
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD=400V, ID = 12A
VGS =10V
69 92 nC
12 nC
31 nC
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
inceases from 0 to 80% VDSS
Table 7. Switching times
Symbol
Parameter
td(on)
tr
Turn-on delay time
Rise time
Test conditions
VDD=250 V, ID=6A,
RG=4.7Ω, VGS=10V
(see Figure 19)
Min. Typ. Max. Unit
24 ns
16 ns
5/19

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P14NK50Z arduino
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STP14NK50Z - STP14NK50ZFP - STB14NK50Z - STB14NK50Z-1 - STW14NK50Z Package mechani-
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/19

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